Clock skew refers to the varying arrival times of the clock signal in synchronous circuits, while slack is the difference between the desired and actual arrival times of a signal. It’s a phenomenon where the clock signal arrives at different components at different times, creating differences in timing within the circuit. This phenomenon is crucial to understand in digital design as it directly impacts the reliability and performance of synchronous circuits.
To illustrate clock skews, let’s consider an example:
Here, we have two flip flops connected in series, and the clock signal is applied to the input of both flip flops. The output of the 1st flip flop is connected to the input of another flip flop. clk1 serves as the clock input for the first flip flop and clk2 as the clock input for the second. Consider, clock input clk is applied to both clock inputs clk1 and clk2. Here, clk will arrive at both clock inputs at different timings. Suppose the clock source clk reaches clk1 at time t and it reaches clk2 at time t+n. Hence, here skew is the difference between the arrival of both clk timings, which is (t+n)-t, which is n. Here, n is the clock skew.
Clock skew can lead to various issues in digital circuits, such as hold time violations and setup time violations, depending on whether the skew is positive or negative. Positive skew occurs when both clock and data are in the same direction, leading to hold time violations but improving setup time violations. Conversely, negative skew occurs when the direction of clock and data is opposite, causing setup time violations but improving hold time violations. Understanding and managing clock skew is essential for ensuring the proper operation and timing integrity of digital designs.
