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9. How Your Electricity Meter Really Works
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22. IoT based project:
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23. Kmaps:
    - Simplifying Boolean Equations with Karnaugh Maps - Part:2 Implicants, Prime Implicants and Essential Prime Implicants. 
    - Simplifying Boolean Equations with Karnaugh Maps - Part:1 Grouping Rules.
    - Simplifying Boolean Equation with Karnaugh Maps.

Verilog Code Examples for Beginners (With Explanation & Testbench)

In this blog post, we’ll delve into some fundamental Verilog code examples that are essential for understanding digital design concepts. Whether you’re new to Verilog or looking to refresh your knowledge, these code snippets will serve as a handy reference for building logic circuits.

1. Logic Gates
2. Half Adder
3. 4-bit Full Adder
4. Half Subtractor
5. Full Subtractor
6. 2:1 Mux
7. 4:1 Mux
8. 2:4 Decoder
9. 3:8 Decoder
10. 4:2 Encoder
11. Priority Encoder
12. Barrel Shifter
13. Comparator
14. BCD to 7 segment Decoder
15. SR Flip Flop
16. D Flip Flop
17. T Flip Flop
18. JK Flip Flop
19. 4-bit ALU
20. Asynchronous Counter
21. Synchronous Counter
22. Up Counter
23. Down Counter
24. Up-Down Counter
25. Mod-N Counter

Happy Coding!

Verilog Code for Mod-N Counter (Mod-10 Example) (With Explanation & Testbench) | #25

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Mod-N Counter in Verilog. A Mod-N counter is a counter that counts from 0 up to (N-1) and then resets back to 0.

This type of counter is widely used in digital systems where a specific counting range is required, such as timers and frequency dividers.

Below is the Verilog code for a Mod-10 Counter, implemented using a Behavioral Modeling approach:

module mod_n_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

parameter N = 10;

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else if (Q == N-1)
    Q <= 4'b0000;
  else
    Q <= Q + 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  mod_n_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%d", $time, Q);

    reset = 1; #10;
    reset = 0;

    #150 $finish;
  end
endmodule

Explanation:

• The counter increments on each rising edge of the clock.
• When the count reaches N-1, it resets back to zero.
• The parameter N defines the modulus of the counter.
• The reset signal initializes the counter to zero.
• This design is flexible and can be modified for any value of N.

Conclusion

This Verilog implementation of a Mod-N Counter demonstrates how controlled counting ranges can be achieved using simple logic. It is widely used in timing circuits and digital applications requiring specific count limits.

What’s Next?

Try implementing Ring Counters and Johnson Counters to explore more advanced counter designs. In the next post, we’ll continue building on sequential logic concepts.

Happy Coding! 🚀

Verilog Code for 4-bit Down Counter (With Explanation & Testbench) | #23

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Down Counter in Verilog. A down counter is a sequential circuit that decrements its output value by one on every clock cycle.

It is commonly used in digital systems for countdown operations, timers, and control logic.

Below is the Verilog code for a 4-bit Down Counter, implemented using a Behavioral Modeling approach:

In this design, the counter decreases its value by one at each rising edge of the clock signal.

module down_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b1111;
  else
    Q <= Q - 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  down_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%b", $time, Q);

    reset = 1; #10;
    reset = 0;

    #100 $finish;
  end
endmodule

Explanation:

• The counter decrements its value by 1 on every rising edge of the clock.
• The reset signal initializes the counter to the maximum value (1111).
• The output Q represents the current count value.
• The counter operates synchronously with the clock signal.
• After reaching the minimum value (0000), it wraps around to 1111.

Conclusion

This Verilog implementation of a Down Counter demonstrates how countdown operations can be implemented using sequential logic. It is widely used in timers and control circuits.

What’s Next?

Try implementing an Up-Down Counter to combine both incrementing and decrementing operations in a single design. In the next post, we’ll explore more advanced counter techniques.

Happy Coding! 🚀

Verilog Code for 4-bit Up-Down Counter (With Explanation & Testbench) | #24

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of an Up-Down Counter in Verilog. An up-down counter is a sequential circuit that can increment or decrement its value based on a control signal.

This type of counter is widely used in digital systems where flexible counting operations are required.

Below is the Verilog code for a 4-bit Up-Down Counter, implemented using a Behavioral Modeling approach:

📊 Block Diagram

(Insert your up-down counter diagram here)

In this design, the direction of counting is controlled by an input signal.

module up_down_counter(
  input clk,
  input reset,
  input mode,   // mode = 1 → up, mode = 0 → down
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else if (mode)
    Q <= Q + 1;
  else
    Q <= Q - 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset, mode;
  wire [3:0] Q;

  up_down_counter uut(clk, reset, mode, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t mode=%b Q=%b", $time, mode, Q);

    reset = 1; #10;
    reset = 0;

    mode = 1; #40; // Up counting
    mode = 0; #40; // Down counting

    #20 $finish;
  end
endmodule

Explanation:

• The counter increments when mode = 1.
• The counter decrements when mode = 0.
• The reset signal initializes the counter to zero.
• The output Q represents the current count value.
• The counter operates synchronously with the clock signal.

Conclusion

This Verilog implementation of an Up-Down Counter demonstrates flexible counting behavior using a simple control signal. It is widely used in applications requiring bidirectional counting.

What’s Next?

Try implementing a Mod-N Counter to control the counting range. In the next post, we’ll explore more advanced counter designs.

Happy Coding! 🚀

Verilog Code for 4-bit Up Counter (With Explanation & Testbench) | #22

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of an Up Counter in Verilog. An up counter is a sequential circuit that increments its output value by one on every clock cycle.

It is widely used in digital systems for counting operations, timing applications, and frequency division.

Below is the Verilog code for a 4-bit Up Counter, implemented using a Behavioral Modeling approach:

In this design, the counter increases its value by one at each rising edge of the clock signal.

module up_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else
    Q <= Q + 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  up_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%b", $time, Q);

    reset = 1; #10;
    reset = 0;

    #100 $finish;
  end
endmodule

Explanation:

• The counter increments its value by 1 on every rising edge of the clock.
• The reset signal initializes the counter to zero.
• The output Q represents the current count value.
• The counter operates synchronously with the clock signal.
• After reaching the maximum value (1111), it wraps around to 0000.

Conclusion

This Verilog implementation of an Up Counter demonstrates a basic counting mechanism using sequential logic. It is widely used in digital systems for timing, sequencing, and control applications.

What’s Next?

Try implementing a Down Counter or Up-Down Counter to explore more flexible counting operations. In the next post, we’ll continue building advanced counter designs.

Happy Coding! 🚀

Verilog Code for Synchronous Counter (With Explanation & Testbench) | #21

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Synchronous Counter in Verilog. A synchronous counter is a sequential circuit where all flip-flops are driven by the same clock signal.

Unlike asynchronous counters, all bits in a synchronous counter change simultaneously on the clock edge, making it faster and more reliable for high-speed applications.

Below is the Verilog code for a 4-bit Synchronous Counter, implemented using a Behavioral Modeling approach:

In the behavioral modeling approach, all bits are updated together using a single clock signal.

module sync_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else
    Q <= Q + 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  sync_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%b", $time, Q);

    reset = 1; #10;
    reset = 0;

    #100 $finish;
  end
endmodule

Explanation:

• The counter increments its value on each rising edge of the clock.
• The reset signal initializes the counter to zero.
• All flip-flops are triggered by the same clock signal.
• This ensures all bits change simultaneously, reducing delay.
• The output Q represents the current count value.

Conclusion

This Verilog implementation of a Synchronous Counter demonstrates a faster and more efficient counting mechanism compared to asynchronous counters. It is widely used in high-speed digital systems.

What’s Next?

Try implementing an Up-Down Counter or Mod-N Counter to explore more advanced counter designs. In the next post, we’ll continue building on sequential logic concepts.

Happy Coding! 🚀

Verilog Code for Asynchronous Counter (Ripple Counter) (With Explanation & Testbench) | #20

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of an Asynchronous Counter in Verilog. An asynchronous counter, also known as a ripple counter, is a sequential circuit where the output of one flip-flop serves as the clock input for the next.

Due to this ripple effect, each flip-flop toggles at different times, making it simple but slightly slower compared to synchronous counters.

Below is the Verilog code for a 4-bit Asynchronous Counter, implemented using a Behavioral Modeling approach:

In the behavioral modeling approach, we use flip-flops where each stage is triggered by the output of the previous stage.

module async_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else
    Q <= Q + 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  async_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%b", $time, Q);

    reset = 1; #10;
    reset = 0;

    #100 $finish;
  end
endmodule

Explanation:

• The counter increments its value on each rising edge of the clock.
• The reset signal initializes the counter to zero.
• The output Q represents the current count value.
• This implementation behaves like a binary counter.
• In real asynchronous counters, each flip-flop is triggered by the previous stage output.

Conclusion

This Verilog implementation of an Asynchronous Counter demonstrates how counting can be achieved using sequential logic. While simple to design, ripple counters introduce propagation delay due to sequential triggering.

What’s Next?

Try implementing a Synchronous Counter to compare performance and timing behavior. In the next post, we’ll explore more counter designs.

Happy Coding! 🚀

Verilog Code for 4-bit ALU (With Explanation & Testbench) | #19

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of an Arithmetic Logic Unit (ALU) in Verilog. An ALU is a fundamental component of digital systems that performs arithmetic and logical operations on binary data.

It is widely used in processors, microcontrollers, and digital signal processing systems.

Below is the Verilog code for a simple 4-bit ALU, implemented using a Behavioral Modeling approach:

In the behavioral modeling approach, we use a case statement to select different operations based on a control signal.

module alu(
  input [3:0] A, B,
  input [2:0] sel,
  output reg [3:0] result,
  output reg carry
);

always @(*)
begin
  case(sel)
    3'b000: {carry, result} = A + B; // Addition
    3'b001: {carry, result} = A - B; // Subtraction
    3'b010: result = A & B;          // AND
    3'b011: result = A | B;          // OR
    3'b100: result = A ^ B;          // XOR
    3'b101: result = ~A;             // NOT
    3'b110: result = A << 1;         // Shift Left
    3'b111: result = A >> 1;         // Shift Right
    default: result = 4'b0000;
  endcase
end

endmodule

🧪 Testbench

module tb_top;
  reg [3:0] A, B;
  reg [2:0] sel;
  wire [3:0] result;
  wire carry;

  alu uut(A, B, sel, result, carry);

  initial begin
    $monitor("Time=%0t A=%b B=%b sel=%b result=%b carry=%b",
              $time, A, B, sel, result, carry);

    A = 4'b0101; B = 4'b0011;

    sel = 3'b000; #10; // Add
    sel = 3'b001; #10; // Sub
    sel = 3'b010; #10; // AND
    sel = 3'b011; #10; // OR
    sel = 3'b100; #10; // XOR
    sel = 3'b101; #10; // NOT
    sel = 3'b110; #10; // Shift Left
    sel = 3'b111; #10; // Shift Right

    #10 $finish;
  end
endmodule

Explanation:

• The ALU performs different operations based on the control signal sel.
• Arithmetic operations include addition and subtraction.
• Logical operations include AND, OR, XOR, and NOT.
• Shift operations move bits left or right.
• The carry output is used for arithmetic operations.

Conclusion

This Verilog implementation of an ALU demonstrates how multiple operations can be integrated into a single module. It is a key building block in processors and digital systems.

What’s Next?

Try extending this ALU by adding more operations or increasing bit width. In the next post, we’ll explore more advanced digital designs and their Verilog implementations.

Happy Coding! 🚀

How Your Electricity Meter Really Works (And What You’re Actually Paying For)

Every time you switch on a light or charge your phone, your electricity meter quietly starts doing calculations in the background. But have you ever wondered what exactly it is measuring — and how that turns into your monthly bill?

When you switch on a light bulb or charge your laptop at home, what you are really doing is using the electrical energy supplied by the electricity distribution system. The power company provides a continuous flow of electric energy, carried by electrons already present in the wires of your home. These electrons don’t come from the power station — they are already in your home wiring — but the power station provides the push, the driving force, that keeps them moving.

Understanding Voltage and Current

That driving force is what we call voltage. In India, for example, our homes typically receive 230 volts AC (alternating current). Voltage is like the electrical pressure that pushes the charges through the circuit.

Along with voltage, we also talk about current, which is the rate of flow of electric charge. So when we say a device consumes 2 amperes, it means electric charge is flowing through it at a rate of 2 coulombs per second, driven by the supply voltage.

What You Are Actually Charged For: Energy

Now, the real physical quantity that your electrical company charges you for is energy, not just current or voltage alone.

Energy (E) is calculated as:

E = P × t

Power (P), in AC systems, is given by:

P = V × I × cosϕ

Where:
cosϕ = power factor

In AC systems, power depends on the power factor, which accounts for the phase difference between voltage and current.

So, energy can be expressed as:

E = V × I × cosϕ × t

If you plug in a 100-watt bulb, it draws a certain current at the given voltage such that the total power is 100 watts. If you leave it on for one hour, the energy consumed is 100 watt-hours (Wh).

That’s why electricity bills are measured in kilowatt-hours (kWh), where:

1 kWh = 1000 watts used for one hour

How Your Energy Meter Works

The electric meter in your house keeps track of this continuously.

It measures voltage and current, calculates power internally, and then integrates it over time to determine energy consumption.

So every fan you run, every light you keep on, and every appliance you use contributes to the total energy consumption. At the end of the billing cycle, you are charged based on the total kilowatt-hours used.

Source and Load: The Complete Picture

When we talk about a voltage source, in your home that is the utility grid. It is connected through transformers and distribution lines and provides an approximately 230 V supply.

Think of it as a reservoir that provides the push.

On the other side is the load.

A load is anything that consumes electrical power — such as a light bulb, fan, heater, refrigerator, or any appliance. When voltage is applied across it, the load draws current.

In simple terms:

• Voltage is provided by the source
• Current depends on the load (its resistance or impedance)

What is Loading?

Loading refers to how much of the source’s capacity is being used by connected devices.

• No Load: No devices are ON → almost no current flows → no power consumed
• Light Load: Only a few small devices are running
• Full Load: System is operating near its maximum capacity

For example:
If your home supply is rated for 100 A and your appliances draw 80 A, you are operating at 80% load.

What Happens During Overloading?

If the load tries to draw more current than the system can safely supply, the system becomes overloaded.

This can lead to overheating, voltage drops, or tripping of protective devices like circuit breakers.

Putting It All Together

In daily life, your home is always connected to the supply line. The source maintains a voltage ready to drive current.

The moment you switch on a device:

• The circuit is completed
• Current begins to flow
• Power is delivered
• Energy starts accumulating

Over time, your energy meter adds all these small amounts of energy consumption together.

And that accumulated energy is what shows up in your monthly bill.

Final Thought

Your electricity meter isn’t just counting units — it is continuously calculating how much electrical work is being done in your home every second.

And by understanding this, you’re not just using electricity — you’re understanding it.