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    - Simplifying Boolean Equation with Karnaugh Maps.

Mastering Verilog: Essential Code Samples for Practice

In this blog post, we’ll delve into some fundamental Verilog code examples that are essential for understanding digital design concepts. Whether you’re new to Verilog or looking to refresh your knowledge, these code snippets will serve as a handy reference for building logic circuits.

1. Logic Gates
2. Half Adder
3. 4-bit Full Adder
4. Half Subtractor
5. Full Subtractor
6. 2:1 Mux
7. 4:1 Mux
8. 2:4 Decoder
9. 3:8 Decoder
10. 4:2 Encoder
11. Priority Encoder
12. Barrel Shifter
13. Comparator
14. BCD to 7 segment Decoder

Happy Coding!

Mastering Verilog: Implementing a Full Subtractor

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Full Subtractor in Verilog. A full subtractor is a combinational circuit used to subtract three bits: two significant bits and a borrow-in, producing a Difference and a Borrow-out.

It is an essential component in digital arithmetic circuits and forms the basis for multi-bit subtraction.

Below is the Verilog code for a Full Subtractor, implemented using a Behavioral Modeling approach:

📊 Block Diagram

Press enter or click to view image in full size

In the behavioral modeling approach, we define the outputs using logical expressions based on the inputs.

module full_subtractor(input a, b, Bin, output D, Bout);
  assign D = a ^ b ^ Bin;
  assign Bout = (~a & b) | (~(a ^ b) & Bin);
endmodule

🧪 Testbench

module tb_top;
  reg a, b, Bin;
  wire D, Bout;
  
  full_subtractor fs(a, b, Bin, D, Bout);
  
  initial begin
    $monitor("At time %0t: a=%b b=%b, Bin=%b, difference=%b, borrow=%b",$time, a,b,Bin,D,Bout);
    a = 0; b = 0; Bin = 0; #1;
    a = 0; b = 0; Bin = 1; #1;
    a = 0; b = 1; Bin = 0; #1;
    a = 0; b = 1; Bin = 1; #1;
    a = 1; b = 0; Bin = 0; #1;
    a = 1; b = 0; Bin = 1; #1;
    a = 1; b = 1; Bin = 0; #1;
    a = 1; b = 1; Bin = 1;
  end
endmodule

Explanation:

• The Difference (D) is calculated using XOR operations among a, b, and Bin.
• The Borrow-out (Bout) is generated when subtraction requires borrowing, based on input conditions.
• The design is purely combinational, meaning outputs change instantly with inputs.
• The testbench verifies all possible input combinations.

Conclusion

This Verilog implementation of a Full Subtractor demonstrates how multi-bit subtraction can be handled using combinational logic. It is a key building block for more complex arithmetic units.

What’s Next?

Try extending this to a multi-bit subtractor and observe borrow propagation across stages. In the next post, we’ll explore more arithmetic circuits and their Verilog implementations.

Happy Coding! 🚀

Mastering Verilog: Implementing a Half Subtractor

 Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Half Subtractor in Verilog. A half subtractor is a combinational circuit used to subtract two single-bit binary numbers and produce a Difference and a Borrow as outputs.
It is a fundamental building block in digital arithmetic circuits.

Below is the Verilog code for a Half Subtractor, implemented using a Behavioral Modeling approach:

📊 Block Diagram

Press enter or click to view image in full size

In the behavioral modeling approach, we define the output using simple logical expressions based on the input values.

module half_subtractor(input a, b, output D, B);
  assign D = a ^ b;
  assign B = ~a & b;
endmodule

🧪 Testbench

module tb_top;
  reg a, b;
  wire D, B;
  
  half_subtractor hs(a, b, D, B);
  
  initial begin
    $monitor("At time %0t: a=%b b=%b, difference=%b, borrow=%b",$time, a,b,D,B);
    a = 0; b = 0;
    #1;
    a = 0; b = 1;
    #1;
    a = 1; b = 0;
    #1;
    a = 1; b = 1;
  end
endmodule

Explanation:

• The Difference (D) is calculated using the XOR operation between inputs a and b.
• The Borrow (B) is generated when a is 0 and b is 1, implemented as ~a & b.
• The design is purely combinational and updates output instantly with input changes.
• The testbench verifies all possible input combinations.

Conclusion

This Verilog implementation of a Half Subtractor demonstrates how basic arithmetic operations can be modeled using simple logic expressions. It serves as a foundation for designing more complex circuits like full subtractors.

What’s Next?

Try extending this design to a Full Subtractor and observe how borrow propagation works. In the next post, we’ll explore more arithmetic circuits and their Verilog implementations.

Happy Coding! 🚀

Mastering Verilog: Implementing a 4-Bit Full Adder

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a 4-bit Full Adder in Verilog. A full adder is a fundamental digital circuit used to perform binary addition, and by combining multiple 1-bit full adders, we can build multi-bit adders.

This design follows a ripple carry architecture, where the carry output from each stage is passed to the next stage.

Below is the Verilog code for a 4-bit Full Adder, implemented using a structural modeling approach:

📊 Block Diagram

Press enter or click to view image in full size

First, we define a 1-bit full adder using logic gate primitives:

// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);// I/O port declarations
output sum, c_out;
input a, b, c_in;// Internal nets
wire s1, c1, c2;// Instantiate logic gate primitives
xor (s1, a, b);
and (c1, a, b);xor (sum, s1, c_in);
and (c2, s1, c_in);or (c_out, c2, c1);endmodule

Next, we build a 4-bit full adder by cascading four 1-bit full adders:

// Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);// I/O port declarations
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;// Internal nets
wire c1, c2, c3;// Instantiate four 1-bit full adders
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);endmodule

Explanation:

• The 1-bit full adder computes sum and carry using basic logic gates (XOR, AND, OR).
• Intermediate signals (s1, c1, c2) help implement the full adder equations.
• The 4-bit adder is built by cascading four 1-bit full adders.
• The carry-out from each stage is connected to the carry-in of the next stage.
• This structure is known as a ripple carry adder, as the carry “ripples” through each stage.

Conclusion

This Verilog implementation of a 4-bit Full Adder demonstrates how complex arithmetic circuits can be built using smaller building blocks. The ripple carry approach is simple and widely used, though it introduces propagation delay as the carry moves through each stage.

What’s Next?

Try simulating this design and observe how carry propagates across stages. In the next post, we’ll explore more efficient adder designs and their Verilog implementations.

Happy Coding! 🚀

Mastering Verilog: Implementing a Priority Encoder

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Priority Encoder in Verilog. A Priority Encoder is a combinational circuit that outputs the binary representation of the highest-priority active input when multiple inputs are high simultaneously.

This type of encoder is widely used in digital systems such as interrupt controllers, arbitration logic, and resource allocation where priority-based decision-making is required.

Below is the Verilog code for a Priority Encoder, implemented using a Behavioral Modeling approach:

📊 Truth Table

Press enter or click to view image in full size

In the behavioral modeling approach, we define priority using ordered conditional statements, where the first true condition gets the highest priority.

module alarm_priority_1 (output [2:0] intruder_zone,
                         output       valid,
                         input  [1:8] zone );assign intruder_zone = zone[1] ? 3'b000 :
                       zone[2] ? 3'b001 :
                       zone[3] ? 3'b010 :
                       zone[4] ? 3'b011 :
                       zone[5] ? 3'b100 :
                       zone[6] ? 3'b101 :
                       zone[7] ? 3'b110 :
                       zone[8] ? 3'b111 :
                       3'b000;assign valid = zone[1] | zone[2] | zone[3] | zone[4] |
               zone[5] | zone[6] | zone[7] | zone[8];endmodule

Explanation:

• The encoder checks inputs from zone[1] to zone[8] in order, assigning priority from lowest index to highest.
• If multiple inputs are high, the first active input in the sequence is selected.
• The intruder_zone output provides the binary index of the highest-priority active input.
• The valid signal indicates whether any input is active.
• If no inputs are active, valid becomes 0 and the output defaults to 000.

Conclusion

This Verilog implementation of a Priority Encoder demonstrates how priority logic can be modeled using simple conditional statements. Such designs are essential in systems where multiple requests compete and only the highest-priority request should be processed.

What’s Next?

Try simulating this design with different input combinations to observe how priority is resolved. In the next post, we’ll explore more advanced digital circuits and their Verilog implementations.

Happy Coding! 🚀