Step-by-step guide on how to design and implement a Mixed-Signal Circuit of 2:1 Multiplexer.

 

• The purpose of this project is to design a Mixed Signal Circuit of 2:1 MUX using an Opensource EDA Tool called eSim and Makerchip software.
• To explore the project, you can git clone using the command: git clone Github.

Table of Contents:

1. Introduction
2. What are Mixed-Signal Circuits?
3. What are Verilog and TL-Verilog?
4. Installation of Tools.
5. Circuit Design
   5.1 Reference Circuit Diagram
   — Digital Block Diagram
   — Analog Block Diagram
   5.2 Reference Circuit Waveform
6. Implementation
7. Reference

1. Introduction

In this project, I am going to Design and Implement a Mixed Signal Circuit of 2:1 Mux. Design and Implementation will be done using esim, and Makerchip software. Mixed-signal circuits contain both Digital and Analog blocks of a given circuit. MUX is a data selector which will give single output from several data inputs. Here we have implemented 2 input MUX which will give single output based on select line input. As this is a mixed-signal circuit we will have complete implementation from HDL code to schematic implementation. We can verify the output using Circuit Waveforms. This complete design and implementation are done using VLSI technology which has features such as high speed, low power, low cost, and small size.

2. What are Mixed-Signal Circuits?

A Mixed-signal integrated circuit is an integrated circuit that has both analog circuits and digital circuits on a single semiconductor die. A signal which continuously varies with time is an Analog Signal. An analog signal can generally be represented as a function of time (f(t)). The signals which are basically generated from nature are analog in nature. Similarly, signals which have discrete values are called Digital signals. These are represented in binary form (0 and 1). Mixed-Signal Circuits contain both analog and digital signals. The below diagram shows a basic block diagram of Mixed-Signal Circuits:

For more information: https://en.wikipedia.org/wiki/Mixed-signal_integrated_circuit

3. What is Verilog and TL-Verilog?

• VERILOG or Verify Logic is a Hardware Description Language commonly used in VLSI Design to create electronic circuits.

For more information: https://en.wikipedia.org/wiki/Verilog

• TL-Verilog or Transaction-Level Verilog is an extension to SystemVerilog that supports a new design methodology, called transaction-level design

For more information: https://www.redwoodeda.com/tl-verilog

4. Installation of Tools.

esim:

esim is an open-source EDA tool used for circuit design and simulation. Using esim we can draw circuits using Kicad, generate netlist and simulate using Ngspice.

For more information: https://esim.fossee.in/home

The download link for the above eSim software is: https://esim.fossee.in/downloads

Makerchip:

Makerchip provides free and instant access to the latest tools from your browser and from your desktop. This includes open-source tools and proprietary ones.

For more information: https://www.makerchip.com/

5. Circuit Design

Multiplexer (MUX) is a data selector which will send single input data at the output based on select line input. Here we have implemented a 2:1 MUX which has 2 inputs (A and B), 1 output (Y), and 1 select line (S). Output Y will be A or B based on 0 or 1 input at the select line (S). If the select line is “0” output Y will be A and if the select line is “1” then output Y will be B. The complete design is divided into two parts Digital Block and Analog Block. Here, we will be using Verilog Hardware Description Language for implementation. We will implement the code using Makerchip software and implement the Circuit schematic using esim software. We know that mixed signals contain both analog and digital blocks hence we need ADC and DAC blocks to convert the signals from analog to digital. Figure 1 shows the Digital Block of the circuit and Figure 2 shows the Circuit Schematic i.e., the Analog Block of the circuit. In the Circuit Waveform, we will verify the above implementation using a clock pulse. Output Y will have the same clock pulse sequence as A when S will be “0” and it will have the same clock pulse sequence as B when S will be “1”.

5.1 Reference Circuit Diagram

• Digital Block Diagram:

• Analog Block Diagram:

5.2 Reference Circuit Waveform

6. Implementation

Step-1:

The Verilog code of 2:1 MUX is as follows:

module radha_mux (input i0 , input i1 , input sel , output reg y);
always @ (*)
begin
if(sel)
y <= i0;
else
y <= i1;
end
endmodule

Initially, we add the Verilog file to Makerchip and run the code to get the expected waveform. Makerchip will itself create a TVL file and run the code.

Below is the .tvl code which will be generated by Makerchip:

\TLV_version 1d: tl-x.org

\SV /* verilator lint_off UNUSED*/ /* verilator lint_off DECLFILENAME*/ /* verilator lint_off BLKSEQ*/ /* verilator lint_off WIDTH*/ /* verilator lint_off SELRANGE*/ /* verilator lint_off PINCONNECTEMPTY*/ /* verilator lint_off DEFPARAM*/ /* verilator lint_off IMPLICIT*/ /* verilator lint_off COMBDLY*/ /* verilator lint_off SYNCASYNCNET*/ /* verilator lint_off UNOPTFLAT / / verilator lint_off UNSIGNED*/ /* verilator lint_off CASEINCOMPLETE*/ /* verilator lint_off UNDRIVEN*/ /* verilator lint_off VARHIDDEN*/ /* verilator lint_off CASEX*/ /* verilator lint_off CASEOVERLAP*/ /* verilator lint_off PINMISSING*/ /* verilator lint_off BLKANDNBLK*/ /* verilator lint_off MULTIDRIVEN*/ /* verilator lint_off WIDTHCONCAT*/ /* verilator lint_off ASSIGNDLY*/ /* verilator lint_off MODDUP*/ /* verilator lint_off STMTDLY*/ /* verilator lint_off LITENDIAN*/ /* verilator lint_off INITIALDLY*/

//Your Verilog/System Verilog Code Starts Here:

module radha_mux (input i0 , input i1 , input sel , output reg y);
always @ (*)
begin
if(sel)
y <= i0;
else
y <= i1;
end
endmodule

//Top Module Code Starts here:

module top(input logic clk, input logic reset, input logic [31:0] cyc_cnt, output logic passed, output logic failed);

logic i0;//input
logic i1;//input
logic sel;//input
logic y;//output

//The $random() can be replaced if user wants to assign values

assign i0 = $random();
assign i1 = $random();
assign sel = $random();
radha_mux radha_mux(.i0(i0), .i1(i1), .sel(sel), .y(y));
\TLV
//Add \TLV here if desired
\SV
endmodule

The below diagram shows the output waveform on the Makerchip window:

Step-2 :

After debugging the Verilog code we open the NgVeri tab and select Add Verilog to NgSpice converter to create the Mux model.

Step-3 :

After successfully creating the model we create the schematic as shown in the below schematic diagram:

Step-4 :

Create netlist and run kicad to ngspice converter. After giving the required timing parameters we will get a .cir.out file.

*/home/radhadk260501/esim-workspace/mixed_circuit_mux/mixed_circuit_mux.cir
*u4 net-u4-pad1 net-u4-pad2 net-u4-pad3 net-u4-pad4 radha_mux
*u5 i0 i1 sel net-u4-pad1 net-u4-pad2 net-u4-pad3 adc_bridge_3
*u6 net-u4-pad4 net-r3-pad1 dac_bridge_1
v1 i0 gnd pulse(0 5 1m 1m 1m 5 10)
v2 i1 gnd pulse(0 5 1m 1m 1m 2.5 5)
v3 sel gnd pulse(0 5 1m 1m 1m 10 20)
*u1 i0 plot_db
*u2 i1 plot_db
r3 net-r3-pad1 y 1k
c1 y gnd 1u
*u7 y plot_db
*u3 sel plot_db
a1 [net-u4-pad1 ] [net-u4-pad2 ] [net-u4-pad3 ] [net-u4-pad4 ] u4
a2 [i0 i1 sel ] [net-u4-pad1 net-u4-pad2 net-u4-pad3 ] u5a3 [net-u4-pad4 ] [net-r3-pad1 ] u6

*Schematic Name: radha_mux, NgSpice Name: radha_mux

.model u4 radha_mux(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )

*Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )

*Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge

.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
.tran 1e-00 40e-00 0e-00
*Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot db(i0)
plot db(i1)
plot db(y)
plot db(sel)
.endc
.end

Step-5 :

Now, we simulate the circuit using NgSpice to verify the logic of the circuit.
We will get waveforms as follows:

The below table shows the Truth Table of 2:1 MUX. We can verify the truth table with the waveform.

In this way, we design and implement a Mixed Signal Circuit.

7. References:

[1] D. S. D. R. A. Rose V Anugraha. Design and performance analysis of 2:1 multiplexer using multiple logic families at 180nmtechnology.https://ieeexplore.ieee.org/abstract/document/8256918.

[2] S. J. Anjum Aara. Design and implementation of CMOS and cnt based 2:1 multiplexer at 32nm technology. www.irjet.net.

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