What are flip-flops and how do they differ from latches?

Flip-flops, like latches, are circuits designed as bistable multivibrators capable of storing one bit of binary data. They retain their state until instructed by an input to change, making them essential in sequential circuits that require memory elements. Unlike latches that lack a clock input and deliver outputs continuously, flip-flops are triggered by clock cycles, defining their operational speed and state transitions.

The key difference between flip-flops and latches lies in their triggering mechanism and behavior. Latches operate without a clock, providing outputs continuously based on input changes. In contrast, flip-flops are synchronized to clock cycles, ensuring stable output changes only at specific clock edges, enhancing their reliability in sequential operations. Below table shows the difference between Flip flops and Latches:

Explore in-depth explanations of flip flops and latches, accompanied by detailed diagrams, by clicking on the links provided below:

1] Latches
2] Flip Flops

Diving into Sequential Circuits: Part 4— Registers

 

• Flip flops are capable of storing 1-bit data, but to store more than 1 bit, registers are required. Registers, which are groups of flip flops, are employed to increase storage capacity. With n flip flops, it is possible to store an n-bit word using a single register.
• Binary data stored in registers can be shifted between flip flops using shift registers.
• A Shift Register is a group of flip flops used to store multiple bits of data and move the data from one flip flop to another. This shifting of data is accomplished using a clock signal. An n-bit shift register requires n flip flops. Shifting can occur either left or right using a Shift Left Register or Shift Right Register.
• Shift registers are classified into the following types:

1. SISO (Serial In Serial Out)
2. SIPO (Serial In Parallel Out)
3. PISO (Parallel In Serial Out)
4. PIPO (Parallel In Parallel Out)
5. Bi-directional Shift Register
6. Universal Shift Register

To gain a deeper understanding of each register, simply click on the corresponding register. Happy Learning!!

Mastering Verilog: Part 5 - Understanding Blocking and Non Blocking Statements

 

• Procedural Statements in Verilog, such as blocking and non-blocking assignments, are categorized as elements of procedural blocks, such as ‘always’ and ‘initial.’
• These statements play a crucial role in updating variables, and once a value is assigned, it remains unchanged until another procedural assignment modifies it. This stands in contrast to continuous assignments, where the value of a variable changes continuously.
• In procedural assignments, the order of signal assignments and the flow of execution are explicitly determined, providing control over the sequencing of operations within the design.
• Procedural blocks in Verilog primarily fall into two categories:

1. always Blocks:
   Usage: Utilized to describe both combinational and sequential logics, triggered by events such as a clock edge (posedge or negedge).
   Example:
   always @(posedge clk) begin
   // Sequential or combinational logic here
   end
2. initial Blocks:
   Usage: Employed to specify initial conditions or setup during simulation, executing once at the beginning.
   Example:
   initial begin
   // Initialization logic here
   end

• Now let us see how these procedural statements work.

1] Blocking assignments:

• Syntax:
  Specified using the ‘=’ operator.
• Execution Flow:
  Statements are executed sequentially in the order specified within the procedural block.
  The execution of subsequent statements is blocked until the current assignment is completed.
• Scope:
  Blocking assignments within one procedural block do not impact the execution of statements in other procedural blocks.
• Example:
  Now let us consider below example to understand how blocking statements work. Below is not the complete verilog code but a module to understand the concept.

integer x,y,z;
initial
begin
x = 20;
y = 15;
z = 30;

x = y + z;
y = x + 10;
z = x — y;
end

Now the output for above logic will be as follows:

initially, x=20,y=15,z=30
x becomes 45
y becomes 55
z becomes -10

• Initial Values:
  Initially, the values of x, y, and z are set to 20, 15, and 30, respectively.
• Execution Steps:
  After the execution of the first statement (x = y + z), the value of x becomes 45.
  The second statement (y = x + 10) utilizes the updated value of x (now 45), resulting in y becoming 55.
  Finally, the third statement (z = x — y) uses the updated values of x (45) and y (55), causing z to become -10.

Provided below is the Verilog code for the logic mentioned above. Experiment with its implementation in simulation software to observe the output.

module blocking_assignment;
reg [31:0] x, y, z;

initial begin
x = 20;
y = 15;
z = 30;

// Blocking assignments
x = y + z; // x is assigned the value of y + z (15 + 30 = 45)
y = x + 10; // y is assigned the value of x + 10 (45 + 10 = 55)
z = x — y; // z is assigned the value of x — y (45–55 = -10)

// Displaying the values after the assignments
$display(“x = %0d, y = %0d, z = %0d”, x, y, z);
end
endmodule

• Now let us consider the same example but with delays:

integer x,y,z;
initial
begin
x = 20;
y = 15;
z = 30;

x = y + z;
#5 y = x + 10;
#10 z = x — y;
end

• Now the output for above logic will be as follows:

initially, x=20,y=15,z=30
x becomes 45
y becomes 55
z becomes -10

• Initial Values:
  Initially, the values of x, y, and z are set to 20, 15, and 30, respectively.
• Execution Steps:
  After the execution of the first statement (x = y + z), the value of x becomes 45.
  At time 0, the second statement (#5 y = x + 10) is scheduled to occur at time 5.
  However, this scheduling doesn’t affect the immediate execution of the next statement.
  At time 0, the third statement (#10 z = x — y) is scheduled to occur at time 10 + 5 = 15.
  This means that the actual execution of the third statement occurs at time 15.
  So, in the scenario with delays, the execution of the third statement (z = x — y) occurs at time 15, not immediately after the second statement. Therefore, the value of z becomes -10 at time 15.

2] Non Blocking Assignment:

• Syntax:
  Specified using the ‘<=’ operator.
• Key Characteristics:
  Non-blocking assignments allow concurrent execution of statements within the same procedural block and do not block the execution of the next statement.
  Particularly suitable for sequential logic implementation in Verilog, commonly used to model flip-flops and other sequential elements in digital circuits.
• Sequential Logic Implementation:
  Non-blocking assignments help avoid race conditions in sequential logic design.
  When multiple signals are updated within the same clocked always block, non-blocking assignments ensure that all updates occur simultaneously at the next clock edge.
• Example:
  Let’s consider the same example used for blocking statements to illustrate how non-blocking statements work:

integer x, y, z;
initial begin
x = 20;
y = 15;
z = 30;

x <= #10 y + z;
y <= #10 x + 10;
z <= #10 x — y;
end

• Output Explanation:
  Initially, the values of x, y, and z are set to 20, 15, and 30.
  After the execution of the statements at time 10 (due to delays), the values become:
  x becomes 45
  y becomes 30
  z becomes -5
• Initially, the values of x, y, and z are set to 20, 15, and 30, respectively.
  According to the given delay (#10), all statements within the initial block will execute at time 10 and will consider the initially defined values for calculation.

In conclusion, the significance of blocking and non-blocking assignments in Verilog coding cannot be overstated. These elements serve as the foundation for precise and effective digital circuit design, offering control over sequential and concurrent execution. As you venture further into the intricacies of Verilog, remember that mastering the art of assignments empowers you to create resilient and optimized digital systems. Happy coding!

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Diving into Sequential Circuits: Part 3 — Counters

• Counters are the sequential circuits which are used to count the pulses. It has input clock signal and group of output signals which display the count value.
• Upon each defined clock edge, it will either increment or decrement the count value. Flip flops are used as memory element. For an N bit counter, the maximum count will be 2^n.
• So if we have 3 bit counter then it will count till value 8. It can be also used as a frequency divider.
• They find applications in various fields such as digital signal processing, frequency division, and general counting tasks in digital systems.
• Based on the input clock signal counters can also be divided as follows:

1. Synchronous: In synchronous counters, all flip flops share a common clock and change their state simultaneously. The changes in the state occur on the rising or falling edge of the clock.
2. Asynchronous: In Asynchronous counters, all flip flops have separate clock and change its state at different times. The clock signals for each flip flop may come from different sources.

• Based on the way of counting counters can be classified as follows:

1. Up Counter: It will start counting from zero to maximum N value.
2. Down Counter: It will start counting from maximum N value to zero value.
3. Up Down Counter: It will act as Up or Down counter based on the select/enable input.

• Now let us consider each counter one by one:

1] Up Counter:

• An Up Counter is an sequential circuit that counts upwards from 0 to the maximum N value. It increments its count on each rising edge(or falling edge depending on the design) of the clock signal. The count sequence is 0,1,2,….,(2^n-1), where n is the number of bits in the counter. Here’s an example of a 3-bit Up Counter:
• So it will initially start at 000 and after the first clock pulse it will increment to 001, after the second clock pulse it will increment to 010 and eventually after the seventh clock pulse it will increment to 111. The counter then resets to 000 on the eighth clock pulse, continuing the clock.
• Now, let’s examine the circuit and operation of a 3-bit up counter. For this, we require three memory elements, and we will be using T flip-flops as the memory elements. The diagram below illustrates the circuit for a 3-bit up counter using T flip-flops.

• Common inputs are provided to all flip-flops, and the input is set to ‘1’. Considering the behavior of T flip-flops, the output toggles when the clock is triggered. We have applied a negative-edge clock, and the output of the first flip-flop is connected to the input clock of the next flip-flop. Q0, Q1, and Q2 are the outputs, where Q0 is the least significant bit (LSB), and Q2 is the most significant bit (MSB).
• To comprehend the operation of the up counter, consider the output waveform below.

• Initially, assume all outputs are zero and plot the three outputs concerning the clock signal. According to the T flip-flop’s operation, the output Q0 toggles at every negative clock edge. For the next flip-flop, Q0’s output serves as the clock signal, toggling at every negative edge of Q0. Similarly, Q1’s output acts as the input clock for the subsequent flip-flop, and Q2’s output toggles with respect to the clock signal. Thus, we have Q0, Q1, and Q2 waveforms. By tracking the states of each output waveform, it becomes evident that the output states follow an increasing order from 0 to 7 (representing the 8 states of a 3-bit counter).

2] Down Counter:

• An Down Counter is an sequential circuit that counts downwards from its maximum value to 0. It decrements its count on each rising edge(or falling edge depending on the design) of the clock signal. The count sequence is (2^n-1),…,2,1,0, where n is the number of bits in the counter.
• Here’s an example of a 3-bit Down Counter:
• So it will initially start at 111 and after the first clock pulse it will increment to 110, after the second clock pulse it will increment to 101 and eventually after the seventh clock pulse it will increment to 000. The counter then resets to 111 on the eighth clock pulse, continuing the clock.
• Now, let’s examine the circuit and operation of a 3-bit down counter. For this, we require three memory elements, and we will be using T flip-flops as the memory elements. The diagram below illustrates the circuit for a 3-bit down counter using T flip-flops.

• Common inputs are provided to all flip-flops, and the input is set to ‘1’. Considering the behavior of T flip-flops, the output toggles when the clock is triggered. We have applied a negative-edge clock, and the output of the first flip-flop is connected to the input clock of the next flip-flop. The only difference in the operation of down counter is that here the output are Q0̅ , Q1̅ and Q2̅ rather than (Q0, Q1, and Q2), where Q0̅ is the least significant bit (LSB), and Q2̅ is the most significant bit (MSB).Consequently, the output waveforms are the exact opposites of those in the up counter, as they represent the complement outputs.
• To comprehend the operation of the Down counter, consider the output waveform below.

• Initially, assume all outputs are zero and plot the three outputs concerning the clock signal. According to the T flip-flop’s operation, the output Q0 toggles at every negative clock edge. For the next flip-flop, Q0’s output serves as the clock signal, toggling at every negative edge of Q0. Similarly, Q1’s output acts as the input clock for the subsequent flip-flop, and Q2’s output toggles with respect to the clock signal. Thus, we have Q0̅ , Q1̅ , and Q2̅ waveforms as the output. By tracking the states of each output waveform, it becomes evident that the output states follow an decreasing order from 7 to 0 (representing the 8 states of a 3-bit counter).

3] Up Down Counter:

• An Up-Down Counter is an sequential circuit that can be configured to act as either an Up Counter or a Down Counter based on a control input. It is also known as a bidirectional counter, is a type of counter that can count both upwards and downwards. It can be used to increment or decrement a count based on a control signal.
  Here’s an example of 3 bit Up-Down counter:
• Let us consider the counter is in the up counting mode:
  So it will initially start at 000 and after the first clock pulse it will increment to 001, after the second clock pulse it will increment to 010 and eventually after the seventh clock pulse it will increment to 111. At this point, the counter reaches its maximum value and rolls over to zero.
• Now lets consider the same counter in the down counting mode:
  So it will initially start at 111 and after the first clock pulse it will increment to 110, after the second clock pulse it will increment to 101 and eventually after the seventh clock pulse it will increment to 000. The counter reaches its minimum value and rolls over to its maximum value.
• The direction (up or down) is controlled by an external signal. When the control signal is set to “up,” the counter increments, and when it’s set to “down,” the counter decrements.
• We previously explored the use of an asynchronous counter for both up and down counting. Now, let’s delve into the workings of an Up-Down counter using a synchronous design.
• The steps outlined below illustrate how to design a Synchronous Up-Down Counter:

1] Identify the Number of Bits, Flip-Flops, and Type of Flip-Flops:
We will employ T flip-flops as memory elements, and for a 3-bit counter, three flip-flops are required, capable of counting up to ²³-1 = 7.

2] Write the Excitation Table of the Flip-Flop:
The excitation table for a T flip-flop is as follows:

3] Operation Based on Control Input M:
Consider the following:
If M = 0, the counter performs up counting.
If M = 1, the counter performs down counting.

4] Draw State Diagram and State Table:
The diagram below depicts the state diagram with eight states.

Based on the input M, states transition from state 0 to state 1 or from state 1 to state 0.
Now, let’s create a state table based on the state diagram. The table includes information about the present state, next state, and the inputs of the flip-flop.
Here, the T value is 1 if there is a change in the output state of a flip-flop (i.e., 0 to 1 and 1 to 0), otherwise 0.

5] Find the Simplified Equations Using K-Maps:
Utilizing K-maps, we derive the equations for T0, T1, and T2.

6] Create a Circuit Diagram:
The diagram below illustrates the circuit for a 3-bit synchronous Up-Down counter. All clock inputs are interconnected, and based on the boolean equations, the T inputs are connected.

7] Output Waveform Depending on the M Signal:
The diagram below showcases the output waveform based on the M signal.

This process outlines the design of a synchronous Up-Down counter.

To gain insights into the implementation of counters using VHDL and Verilog, please visit the link provided below.
1) VHDL
2) Verilog

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