Parallel In Serial Out (PISO) Shift Register

 

PISO (Parallel In Serial Out):

• The Parallel-In-Serial-Out (PISO) shift register is a digital circuit that accepts parallel input data and produces a serial output. In contrast to the Serial-In-Parallel-Out (SIPO) shift register, the PISO configuration is useful when data needs to be shifted out serially while being presented in parallel at the input. Consider a 4-bit PISO shift register using D flip-flops.
  

• Initially, all flip-flops are reset (Q3=Q2=Q1=Q0=0). If the parallel input data is 1011, each bit is simultaneously applied to the corresponding flip-flop inputs. Illustrated below is a 4-bit SIPO shift register utilizing D flip-flops. Here, Output of previous Flip Flop is connected to the input of the next one via a combinational circuit. Here we also have shift/Load bar terminal in the circuit digaram.
• In Parallel-In-Serial-Out (PISO) shift registers, there are two primary modes of operation: the “load” mode and the “shift” mode. These modes determine how data is handled in the shift register.
• Let’s consider a 4-bit PISO shift register in both load and shift modes:

1. Load Mode:
   In the load mode, the PISO shift register accepts parallel input data. During this mode, the parallel input data is loaded into the flip-flops simultaneously. Each flip-flop stores one bit of the parallel input data. This mode is typically activated by a control signal (e.g., Load/Shift control). Initialize all flip-flops to a reset state: Q3 Q2 Q1 Q0 = 0000. Apply parallel input data (e.g., 1011) to the flip-flop inputs.
   Activate the load control signal. On the rising or falling edge of the clock, the parallel input data is loaded into the flip-flops.
   Result after load: Q3 Q2 Q1 Q0 = 1011.
2. Shift Mode:
   In the shift mode, the PISO shift register shifts the stored data out serially. The stored parallel data is shifted out bit by bit, starting from the Most Significant Bit (MSB) to the Least Significant Bit (LSB).
   This mode is activated by a different control signal or the absence of a load signal. The shifting occurs on each clock edge, either rising or falling, depending on the design. Deactivate the load control signal (or activate the shift control signal). On each subsequent clock edge, the stored data is shifted out serially. Result after shift: Serial output = 1011.

• Now, let’s delve into the operational transition of the combinational circuit as it switches from the load mode to the shift mode.
• In the configuration, there is a Shift/Load bar terminal with two lines, one of which is connected to a NOT gate, providing inverse inputs to both lines. A circuit, comprising one OR gate and two AND gates, is interlinked. Pay close attention to the connections: notice how the output of the first flip-flop is linked to the input of an AND gate, and how the Shift/Load lines are connected to the AND gates, along with input lines B3, B2, B1, and B0. Initially, the shift register operates in load mode to load the data. For the Parallel-In-Serial-Out (PISO) shift register to function in load mode, the Shift/Load bar input must be 0, and for it to operate in shift mode, it must be 1.
• Refer to the diagram below, where the AND gates receive input values based on the shift/load input. Following the logic of AND gates, if any input is 0, the output is 0. Consequently, the output of AND gates 1, 3, 5 will be 0. Conversely, if any input is 1, the other terminal serves as the output. Thus, the output of AND gates 2, 4, 6 will be B2, B1, B0, respectively. Following the logic of the OR gate, the output of OR gate 1, 2, 3 will be B2, B1, B0, respectively. This output is then fed into the input of the flip-flop. Flip-flop 1 directly takes the input B3. This process facilitates loading the input B3B2B1B0 into the flip-flops. Subsequently, after the clock input, the input data is available at the output, resulting in Q3Q2Q1Q0 = B3B2B1B0.

• During shift mode, the Shift/Load bar terminal is set to 1. The diagram illustrates how the AND gates receive inputs based on the shift/load line inputs. According to the AND gate’s operation, the output of AND gates 2, 4, 6 will be 0, and the output of AND gates 1, 3, 5 will be Q3Q2Q1. Following the OR gate’s logic, the output of OR gate 1, 2, 3 will be Q3Q2Q1, respectively. This output is then connected to the input of the flip-flop, facilitating the shift of data in the PISO shift register.