Showing posts with label DYNAMIC. Show all posts
Showing posts with label DYNAMIC. Show all posts

September 7, 2024

Explore Our Topics!

Check out the extensive list of topics we discuss: 

  1. Communication Protocols:
    USB 
    - RS232 
    Ethernet 
    AMBA Protocol: APB, AHB and ASB 
    UART, I2C AND SPI
  2. Important concepts in VLSI:
    Designing a Chip? Here Are the 12 Important Concepts You Need to Know
    Metastability 
    - Setup time and Hold time
    Signal Integrity and Crosstalk effect
    Skews and Slack 
    Antenna Effect
  3. Semiconductor Memories
  4. Most Frequently Asked Questions in VLSI
  5. Transistors:
    BJT
    JFET
    MOSFET
    CMOS
    Transmission Gate CMOS
    Dynamic CMOS
  6. Sequential Circuits:
    Registers
    Counters
    Latches
    Flip Flops
  7. FPGA:
    ASIC vs FPGA
    FPGA Insights: From Concept to Configuration
    Full-Custom and Semi-Custom VLSI Designs: Pros, Cons and differences
    From Theory to Practice: CMOS Logic Circuit Design Rules Made Easy with Examples
  8. CMOS Fabrication:
    CMOS Fabrication
    Twin-Tub CMOS Technology
  9. Combinational Circuits
    - Logic Gates 
    - Boolean Algebra and DeMorgan's Law 
    - Multiplexer (MUX) and Demultiplexer (DEMUX) 
    - Half Adder
    - Full Adder
    - Half Subtractor
    - Full Subtractor
  10. Verilog
    - Verilog Datatypes
    - Comments, Numeral Formats and Operators
    - Modules and Ports
    - assign, always and initial keywords
    Blocking and Non-Blocking Assignments
    - Conditional Statements
    - Looping Statements
    - break and continue Statement
    - Tasks and Functions
    - Parameter and generate
    - Verilog Codes
  11. System Verilog: 
    Disable fork and Wait fork.
    Fork and Join.
  12. Project on Intel Quartus Prime and Modelsim:
    Vending Machine Controller
  13. Xilinx Vivado Projects
    1)VHDL
    Counters using Testbench code
    Flip Flops using Testbench code
    Logic Gates using Testbench code
    Full Adder using Half Adder and Testbench code
    Half Adder using Testbench code
    2)Verilog
    Logic Gates using Testbench code
    Counters using Testbench code
    Full Adder using Half Adder and Testbench code
    Half Adder using Testbench code
  14. VLSI Design Flow:
    Design Flow in VLSI
    Y chart or Gajski Kuhn Chart
  15. Projects on esim:
    Step-by-Step guide on how to Design and Implement a Full Adder using CMOS and sky130nm PDK
    Step-by-Step guide on how to Design and Implement a Half Adder using CMOS and sky130nm PDK
    Step-by-Step guide on how to Design and Implement a 2:1 MUX using CMOS and sky130nm PDK
    Step-by-Step guide on how to Design and Implement a Mixed-Signal Circuit of 2:1 Multiplexer
  16. IoT based project:
    Arduino
    Step-by-Step guide on how to Interface Load Cell using Arduino
  17. Kmaps:
    Simplifying Boolean Equations with Karnaugh Maps - Part:2 Implicants, Prime Implicants and Essential Prime Implicants. 
    Simplifying Boolean Equations with Karnaugh Maps - Part:1 Grouping Rules.
    Simplifying Boolean Equation with Karnaugh Maps.

Explore Our Topics!

Check out the extensive list of topics we discuss:  Communication Protocols: -  USB   - RS232   -  Ethernet   -  AMBA Protocol: APB, AHB and...