The Impact of Metastability on Digital Circuits: Flip Flops Unveiled

• Metastability in flip-flops can be defined as the state when the output of the flip-flop oscillates between high and low values. It can be understood using setup time and hold time.
• The concept of setup time and hold time mainly occurs while performing static timing analysis.
• Let us consider an example of flip flop to understand setup time and hold time and why they are important in understanding metastability.



1] Consider a D flip flop as shown in the above diagram. Here, input D is given to the flip flop, Q is the output, and clk is the clock cycle.
2] In the waveform shown above, region one is the setup time region and region two is the hold time region.
3] The setup time is the interval before the clock where the data must be held stable for the data to be latched correctly. Similarly, hold time is the interval after the clock where the data must be held stable.
4] Here, the input D must remain stable and not change in the setup time before the clock occurs and it must also remain stable after the clock edge has occurred in region two i.e., during hold time.
5] Aperture time can be defined as the total interval where input must remain stable which is setup time + hold time hence the flip flop must be stable during its aperture time.

• But why should it remain stable?

To understand this, we will consider 3 states as follow:

1] Consider that the input of the flip flop is stable for low value during aperture time. Then the output will take a low value. Similarly, if the input of the flip flop is high in the aperture time, then the output will take a high value. This can be seen in the below diagram:



2] But if the input of the flip flop changes to a high or low value during the aperture time then the flip flop captures a value partway between low and high and this state is called the Metastable state or Quasi-stable state. This can be summarized in the below diagram.



The output will eventually take a high or a low value, but it will unlimited amount of time to settle or resolve to a good high or low value.

This process of flip-flop going into a metastable state and then getting into a high or a low state is called metastability.

• Causes:

1] Set up time and hold time are not met for the system.
2] If the input to flip flop is asynchronous.
3] Input through a button or two flip flops connected together with the same frequency but in different phases.

• Why is it important?

1] Consider if two flip flops are connected one after the other as shown in the below diagram and output of 1st flip flop is given as input to the other flip flop. If the first flip-flop goes into a metastable state and cannot resolve the output to a low or high value then it will cause an error for the next flip-flop.



• Solution:

1] Resolution Time (Tres):
The time taken by the flip flop to resolve into a high or low state, measured from the clock edge is called as Resolution time (Tres).
The below diagrams show the resolution time.



The longer the resolution time greater is the chance for our system to fail.

2] Synchronizer:
Synchronizers use the concept of resolution time to ensure only good and stable logics goes into the system. Synchronizer uses an asynchronous input D, clock, and output Q which is synchronous with the systems clock domain.



If the input D is stable during the aperture time, the output of synchronizer Q will be equal to D but if D is changing during aperture time Q can be either zero or one but must not be in a metastable state in this way a synchronizer works.

Let us understand synchronizer by considering an example:



A simple synchronizer can be made using two flip flops connecting back-to-back having the same clock as this system. If D is stable during aperture time D2 and Q will be equal to D after one clock cycle. But if input D changes during aperture time D2 will go into the metastable state if the time Tc is large enough then D2 will resolve into a stable value with high probability. The 2nd flip flop will now sample D2 which is stable so Q will be stable. Here, Tres is the resolution time.

If D2 doesn’t resolve into any stable or valid value during time Tc it will cause Q to go into a metastable state and the synchronizer will fail.

MTBF — mean time between failure:
This indicates how often the given design can fail, i.e., what is the average time between two successive failures it should be as high as possible.

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