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2. Important concepts in VLSI:
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4. Most Frequently Asked Questions in VLSI
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8. CMOS Fabrication:
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12. Project on Intel Quartus Prime and Modelsim:
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13. Xilinx Vivado Projects
    1)VHDL
    - Counters using Testbench code
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    - Half Adder using Testbench code
    2)Verilog
    - Logic Gates using Testbench code
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    - Full Adder using Half Adder and Testbench code
    - Half Adder using Testbench code
14. VLSI Design Flow:
    - Design Flow in VLSI
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15. Projects on esim:
    - Step-by-Step guide on how to Design and Implement a Full Adder using CMOS and sky130nm PDK
    - Step-by-Step guide on how to Design and Implement a Half Adder using CMOS and sky130nm PDK
    - Step-by-Step guide on how to Design and Implement a 2:1 MUX using CMOS and sky130nm PDK
    - Step-by-Step guide on how to Design and Implement a Mixed-Signal Circuit of 2:1 Multiplexer
16. IoT based project:
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    - Step-by-Step guide on how to Interface Load Cell using Arduino
17. Kmaps:
    - Simplifying Boolean Equations with Karnaugh Maps - Part:2 Implicants, Prime Implicants and Essential Prime Implicants. 
    - Simplifying Boolean Equations with Karnaugh Maps - Part:1 Grouping Rules.
    - Simplifying Boolean Equation with Karnaugh Maps.

Verilog - NOT Gate

 not_gate.v

module and_gate(a,y);
input a;
output y;

not(y,a);
endmodule

tb_not_gate.v

module tb_not_gate;
reg a;
wire y;

not_gate UUT (.a(a), .y(y));

initial begin
$display(“Testing NOT gate”);

a = 0;
#10;
$display(“Input_A = %b, Output = %b”, a,y);

a = 1;
#10;
$display(“Input_A = %b, Output = %b”, a,y);

$finish;
end
endmodule

The output waveform for not gate will be as follows:

Verilog - XNOR Gate

 xnor_gate.v

module xnor_gate(a,b,y);
input a;
input b;
output y;

xnor(y,a,b);
endmodule

tb_xnor_gate.v

module tb_xnor_gate;
reg a;
reg b;
wire y;

xnor_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display(“Testing XNOR gate”);

a = 0; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 0; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

$finish;
end
endmodule

The output waveform for xnor gate will be as follows:

Verilog - XOR Gate

 xor_gate.v

module xor_gate(a,b,y);
input a;
input b;
output y;

xor(y,a,b);
endmodule

tb_xor_gate.v

module tb_xor_gate;
reg a;
reg b;
wire y;

xor_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display(“Testing XOR gate”);

a = 0; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 0; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

$finish;
end
endmodule

The output waveform for xor gate will be as follows:

Verilog - NOR Gate

 nor_gate.v

module nor_gate(a,b,y);
input a;
input b;
output y;

nor(y,a,b);
endmodule

tb_nor_gate.v

module tb_nor_gate;
reg a;
reg b;
wire y;

nor_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display(“Testing NOR gate”);

a = 0; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 0; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

$finish;
end
endmodule

The output waveform for nor gate will be as follows:

Verilog - NAND Gate

 nand_gate.v

module nand_gate(a,b,y);
input a;
input b;
output y;

nand(y,a,b);
endmodule

tb_nand_gate.v

module tb_nand_gate;
reg a;
reg b;
wire y;

nand_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display("Testing NAND gate");

a = 0; b=0;
#10;
$display("Input_A = %b, Input_B = %b, Output = %b", a,b,y);

a = 0; b=1;
#10;
$display("Input_A = %b, Input_B = %b, Output = %b", a,b,y);

a = 1; b=0;
#10;
$display("Input_A = %b, Input_B = %b, Output = %b", a,b,y);

a = 1; b=1;
#10;
$display("Input_A = %b, Input_B = %b, Output = %b", a,b,y);

$finish;
end
endmodule

The output waveform for nand gate will be as follows:

Verilog - Or Gate

 or_gate.v

module or_gate(a,b,y);
input a;
input b;
output y;

or(y,a,b);
endmodule

tb_or_gate.v

module tb_or_gate;
reg a;
reg b;
wire y;

or_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display(“Testing OR gate”);

a = 0; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 0; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

$finish;
end
endmodule

The output waveform for or gate will be as follows:

Step-by-step guide on how to design and implement Logic Gates with testbench code on Xilinx Vivado design tool using Verilog HDL.

 In this project, we will see how to implement all logic gates with verilog testbench code on Xilinx Vivado design tool. Below diagram shows all logic gates along with there truth tables, symbol and Boolean equation.

Now let us see how we will implement these gates using Xilinx Vivado design tool.

Step 1: Click on New Project -> Next

Step 2: Enter Project Name and Select appropriate Project Location -> Next

Step 3: Select RTL Project -> Next

Step 4: Click on Create File and create file with file name and_gate -> Next

Step 5: We will not add the Constraint file So click on Next

Step 6: For Default Part click on Next as we are not using any development Board

Step 7: Check the New Project Summary and click on Finish.

Step 8: Now you will be prompted with the Define module page but we will create the complete code from scratch so click on cancel and Yes

Step 9: Now on the Home Page click on Sources -> Design Sources -> Non-module Files

Step 10: Enter the below codes in the “and_gate.v” files.

and_gate.v

module and_gate(a,b,y);
input a;
input b;
output y;

and(y,a,b);
endmodule

Step 11: Now to write the testbench code for and gate right click on Design Sources -> Add Sources -> Add or create design sources -> Create File -> Add File name as tb_and_gate -> Finish -> Ok -> Yes

Step 12: Now open the testbench file and enter the below testbench code

module tb_and_gate;
reg a;
reg b;
wire y;

and_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display(“Testing AND gate”);

a = 0; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 0; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

$finish;
end
endmodule

Here, in testbench code we do not define values in entity hence we have kept it empty. Then in architecture we have copied the components of and_gate and defined signals for connecting the ports of and gate. Inside the process statement we write all 4 test cases from truth table and define the delay as 100ns.

Step 13: Now as we have written all the codes let’s launch the simulation. Enter launch_simulation in the Tcl Console and press Enter.

We have successfully implemented and gate with testbench code. Click on Zoom Fit to see the output waveform more clearly and verify the outputs.

If we want to implement other gates the process will be same except the Verilog codes. Visit below links to see how to implement other gates:

1] Or Gate

2] Nand Gate

3] Nor Gate

4] Xor Gate

5] Xnor Gate

6] Not Gate

In this way, we can implement all logic gates using testbench codes.

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