Verilog - XOR Gate

 xor_gate.v

module xor_gate(a,b,y);
input a;
input b;
output y;

xor(y,a,b);
endmodule

tb_xor_gate.v

module tb_xor_gate;
reg a;
reg b;
wire y;

xor_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display(“Testing XOR gate”);

a = 0; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 0; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

$finish;
end
endmodule

The output waveform for xor gate will be as follows: