not_gate.v
module and_gate(a,y);
input a;
output y;
not(y,a);
endmodule
tb_not_gate.v
module tb_not_gate;
reg a;
wire y;
not_gate UUT (.a(a), .y(y));
initial begin
$display(“Testing NOT gate”);
a = 0;
#10;
$display(“Input_A = %b, Output = %b”, a,y);
a = 1;
#10;
$display(“Input_A = %b, Output = %b”, a,y);
$finish;
end
endmodule
The output waveform for not gate will be as follows:
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