Diving into Sequential Circuits: Part 4— Registers

 

• Flip flops are capable of storing 1-bit data, but to store more than 1 bit, registers are required. Registers, which are groups of flip flops, are employed to increase storage capacity. With n flip flops, it is possible to store an n-bit word using a single register.
• Binary data stored in registers can be shifted between flip flops using shift registers.
• A Shift Register is a group of flip flops used to store multiple bits of data and move the data from one flip flop to another. This shifting of data is accomplished using a clock signal. An n-bit shift register requires n flip flops. Shifting can occur either left or right using a Shift Left Register or Shift Right Register.
• Shift registers are classified into the following types:

1. SISO (Serial In Serial Out)
2. SIPO (Serial In Parallel Out)
3. PISO (Parallel In Serial Out)
4. PIPO (Parallel In Parallel Out)
5. Bi-directional Shift Register
6. Universal Shift Register

To gain a deeper understanding of each register, simply click on the corresponding register. Happy Learning!!

Mastering Verilog: Part 5 - Understanding Blocking and Non Blocking Statements

 

• Procedural Statements in Verilog, such as blocking and non-blocking assignments, are categorized as elements of procedural blocks, such as ‘always’ and ‘initial.’
• These statements play a crucial role in updating variables, and once a value is assigned, it remains unchanged until another procedural assignment modifies it. This stands in contrast to continuous assignments, where the value of a variable changes continuously.
• In procedural assignments, the order of signal assignments and the flow of execution are explicitly determined, providing control over the sequencing of operations within the design.
• Procedural blocks in Verilog primarily fall into two categories:

1. always Blocks:
   Usage: Utilized to describe both combinational and sequential logics, triggered by events such as a clock edge (posedge or negedge).
   Example:
   always @(posedge clk) begin
   // Sequential or combinational logic here
   end
2. initial Blocks:
   Usage: Employed to specify initial conditions or setup during simulation, executing once at the beginning.
   Example:
   initial begin
   // Initialization logic here
   end

• Now let us see how these procedural statements work.

1] Blocking assignments:

• Syntax:
  Specified using the ‘=’ operator.
• Execution Flow:
  Statements are executed sequentially in the order specified within the procedural block.
  The execution of subsequent statements is blocked until the current assignment is completed.
• Scope:
  Blocking assignments within one procedural block do not impact the execution of statements in other procedural blocks.
• Example:
  Now let us consider below example to understand how blocking statements work. Below is not the complete verilog code but a module to understand the concept.

integer x,y,z;
initial
begin
x = 20;
y = 15;
z = 30;

x = y + z;
y = x + 10;
z = x — y;
end

Now the output for above logic will be as follows:

initially, x=20,y=15,z=30
x becomes 45
y becomes 55
z becomes -10

• Initial Values:
  Initially, the values of x, y, and z are set to 20, 15, and 30, respectively.
• Execution Steps:
  After the execution of the first statement (x = y + z), the value of x becomes 45.
  The second statement (y = x + 10) utilizes the updated value of x (now 45), resulting in y becoming 55.
  Finally, the third statement (z = x — y) uses the updated values of x (45) and y (55), causing z to become -10.

Provided below is the Verilog code for the logic mentioned above. Experiment with its implementation in simulation software to observe the output.

module blocking_assignment;
reg [31:0] x, y, z;

initial begin
x = 20;
y = 15;
z = 30;

// Blocking assignments
x = y + z; // x is assigned the value of y + z (15 + 30 = 45)
y = x + 10; // y is assigned the value of x + 10 (45 + 10 = 55)
z = x — y; // z is assigned the value of x — y (45–55 = -10)

// Displaying the values after the assignments
$display(“x = %0d, y = %0d, z = %0d”, x, y, z);
end
endmodule

• Now let us consider the same example but with delays:

integer x,y,z;
initial
begin
x = 20;
y = 15;
z = 30;

x = y + z;
#5 y = x + 10;
#10 z = x — y;
end

• Now the output for above logic will be as follows:

initially, x=20,y=15,z=30
x becomes 45
y becomes 55
z becomes -10

• Initial Values:
  Initially, the values of x, y, and z are set to 20, 15, and 30, respectively.
• Execution Steps:
  After the execution of the first statement (x = y + z), the value of x becomes 45.
  At time 0, the second statement (#5 y = x + 10) is scheduled to occur at time 5.
  However, this scheduling doesn’t affect the immediate execution of the next statement.
  At time 0, the third statement (#10 z = x — y) is scheduled to occur at time 10 + 5 = 15.
  This means that the actual execution of the third statement occurs at time 15.
  So, in the scenario with delays, the execution of the third statement (z = x — y) occurs at time 15, not immediately after the second statement. Therefore, the value of z becomes -10 at time 15.

2] Non Blocking Assignment:

• Syntax:
  Specified using the ‘<=’ operator.
• Key Characteristics:
  Non-blocking assignments allow concurrent execution of statements within the same procedural block and do not block the execution of the next statement.
  Particularly suitable for sequential logic implementation in Verilog, commonly used to model flip-flops and other sequential elements in digital circuits.
• Sequential Logic Implementation:
  Non-blocking assignments help avoid race conditions in sequential logic design.
  When multiple signals are updated within the same clocked always block, non-blocking assignments ensure that all updates occur simultaneously at the next clock edge.
• Example:
  Let’s consider the same example used for blocking statements to illustrate how non-blocking statements work:

integer x, y, z;
initial begin
x = 20;
y = 15;
z = 30;

x <= #10 y + z;
y <= #10 x + 10;
z <= #10 x — y;
end

• Output Explanation:
  Initially, the values of x, y, and z are set to 20, 15, and 30.
  After the execution of the statements at time 10 (due to delays), the values become:
  x becomes 45
  y becomes 30
  z becomes -5
• Initially, the values of x, y, and z are set to 20, 15, and 30, respectively.
  According to the given delay (#10), all statements within the initial block will execute at time 10 and will consider the initially defined values for calculation.

In conclusion, the significance of blocking and non-blocking assignments in Verilog coding cannot be overstated. These elements serve as the foundation for precise and effective digital circuit design, offering control over sequential and concurrent execution. As you venture further into the intricacies of Verilog, remember that mastering the art of assignments empowers you to create resilient and optimized digital systems. Happy coding!

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Inside the USB: Mastering USB Protocol for Tech Enthusiasts

 USB, which stands for Universal Serial Bus, is an asynchronous communication protocol enabling data exchange and power transfer among electronic devices. Originally developed by Compaq, DEC, IBM, Intel, Microsoft, NEC, and Nortel, USB aims to standardize the connection of peripherals, such as mice, keyboards, printers, etc., to computer systems.

• The different types of USB versions are as follows:

• USB connectors come in various shapes and sizes, each designed for specific purposes. Here are some common types of USB connectors:

1. USB Type-A
2. USB Type-B
3. USB Type-C
4. USB Mini
5. USB Micro
6. USB 3.0

• Working:

1. USB operates with a host-slave architecture, where the computer acts as the host or master, and connected peripherals are slaves.
2. It supports up to 127 devices due to its 7-bit addressing.
3. USB is asynchronous, eliminating the need for a clock signal.
4. Here, host can only initiate the Data transfer.
5. Now to understand the working let us consider USB type A and USB type B.
6. Below digaram shows internal pins of Type A and Type B USB.

The USB connector features four pins (1, 2, 3, 4), with Pin 1 and Pin 4 designated for Vcc (power supply) and Gnd (ground), while Pin 2 and Pin 3 carry D- (data negative) and D+ (data positive) signals. The D+ and D- signals convey the same data, albeit in a mirrored fashion. At the receiver side, a differential amplifier calculates the disparity between D+ and D-, providing a robust mechanism for noise immunity.

USB devices boast hot swapping and plug-and-play capabilities. Hot swapping enables users to connect or disconnect devices while the system is operational, while plug and play ensures that the operating system autonomously identifies and configures connected devices, eliminating the need for manual intervention. The processor continuously monitors the state of I/O devices to facilitate seamless data transmission, relieving I/O devices from the responsibility of updating the processor.

When a new I/O device connects to the hub, it is assigned the address ‘0.’ Subsequently, when the host establishes a connection with the new device, it assesses the device’s capabilities and selects a suitable driver for communication. This dynamic process ensures efficient and tailored communication between the host and the connected I/O devices.

• USB Architecture:

The diagram below illustrates the architecture of the USB protocol, which operates on a Tree Topology.

In this configuration, a single host serves as the central point, and multiple slave devices can be connected to it. I/O devices establish connections with the computer through a Hub, creating a tree-like structure. The Hub functions as the nexus for connecting both I/O devices and the computer, facilitating an organized and efficient network topology.

• USB data format:

In USB communication, data is transferred in the form of packets, categorized into four main types: Token, Data, Handshake, and Start of Frame. To facilitate effective data transmission, USB adheres to a specific message format outlined below:

1. SYNC: Every USB packet initiates with a SYNC field, an 8-bit segment utilized for synchronizing the transmitter and receiver to facilitate data transmission.
2. Packet Identifier Field (PID): The PID field within the USB protocol serves to identify the type of packet being transmitted. This 8-bit field consists of upper 4 bits indicating the packet type and lower 4 bits representing the bitwise complement of the upper 4 bits.
3. Address Field: The address field specifies the address of the USB device involved in the communication. Each USB device connected to a bus is assigned a unique address. The 7-bit address field in a token packet allows for up to 127 unique device addresses.
4. Endpoint Field: The endpoint field directs data transfers to and from specific endpoints on a USB device, identified by their endpoint numbers. This 4-bit field in a token packet represents up to 16 different endpoints (0 to 15), with endpoint 0 reserved for configuration, status, and control operations. Additionally, the endpoint field indicates the direction of data transfer — host to device or device to host.
5. Data Field: The data field carries the actual information being transferred between the USB host (typically a computer) and the USB device. The length of the data field is not fixed and ranges from 0 to 8192 bits.
6. CRC (Cyclic Redundancy Check): CRC is an error-checking mechanism crucial for ensuring the integrity of transmitted data in the USB protocol. It assists the receiver in verifying that the received data matches the original data sent by the transmitting end.
7. EOP field: The End of Packet (EOP) field is used to indicate the conclusion of a packet and prepares for the start of the next one, ensuring a well-defined boundary between successive packets.

• Applications of USB Protocol:

1. Computer Peripherals: USB is extensively used for connecting a diverse range of computer peripherals, including keyboards, mice, printers, scanners, webcams, and external hard drives.
2. Storage: Many hard drives leverage the USB protocol for efficient data transfer, storage, and transportation.
3. Smartphones: USB is a key technology for smartphones, serving dual purposes for charging and data transfer between mobile devices and other peripherals.
4. Cameras and Webcams: Cameras, webcams, and video streaming devices utilize USB for data transfer and control. USB connections provide a reliable means for transferring multimedia content and enabling communication between imaging devices and computers.
5. Gaming Peripherals: USB is commonly employed for connecting gaming peripherals such as controllers, joysticks, and other input devices.
6. Industries: USB finds applications in industrial settings, particularly in the connection of sensors, actuators, and other industrial equipment. Its standardized interface simplifies integration and communication in diverse industrial applications.
7. Medical Devices: USB is utilized in the medical field to connect various medical devices to computers for data transfer and communication. It ensures a reliable and standardized interface for exchanging data between medical equipment and computer systems, facilitating healthcare operations.

Do explore my other blogs covering the following communication protocols:

1. AMBA, APB, AHB and ASB
2. UART, I2C, and SPI
3. Ethernet

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Verilog - NOT Gate

 not_gate.v

module and_gate(a,y);
input a;
output y;

not(y,a);
endmodule

tb_not_gate.v

module tb_not_gate;
reg a;
wire y;

not_gate UUT (.a(a), .y(y));

initial begin
$display(“Testing NOT gate”);

a = 0;
#10;
$display(“Input_A = %b, Output = %b”, a,y);

a = 1;
#10;
$display(“Input_A = %b, Output = %b”, a,y);

$finish;
end
endmodule

The output waveform for not gate will be as follows:

Verilog - XNOR Gate

 xnor_gate.v

module xnor_gate(a,b,y);
input a;
input b;
output y;

xnor(y,a,b);
endmodule

tb_xnor_gate.v

module tb_xnor_gate;
reg a;
reg b;
wire y;

xnor_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display(“Testing XNOR gate”);

a = 0; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 0; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

$finish;
end
endmodule

The output waveform for xnor gate will be as follows:

Verilog - XOR Gate

 xor_gate.v

module xor_gate(a,b,y);
input a;
input b;
output y;

xor(y,a,b);
endmodule

tb_xor_gate.v

module tb_xor_gate;
reg a;
reg b;
wire y;

xor_gate UUT (.a(a), .b(b), .y(y));

initial begin
$display(“Testing XOR gate”);

a = 0; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 0; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=0;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

a = 1; b=1;
#10;
$display(“Input_A = %b, Input_B = %b, Output = %b”, a,b,y);

$finish;
end
endmodule

The output waveform for xor gate will be as follows: