- Procedural Statements in Verilog, such as blocking and non-blocking assignments, are categorized as elements of procedural blocks, such as ‘always’ and ‘initial.’
- These statements play a crucial role in updating variables, and once a value is assigned, it remains unchanged until another procedural assignment modifies it. This stands in contrast to continuous assignments, where the value of a variable changes continuously.
- In procedural assignments, the order of signal assignments and the flow of execution are explicitly determined, providing control over the sequencing of operations within the design.
- Procedural blocks in Verilog primarily fall into two categories:
- always Blocks:
Usage: Utilized to describe both combinational and sequential logics, triggered by events such as a clock edge (posedge or negedge).
Example:
always @(posedge clk) begin
// Sequential or combinational logic here
end - initial Blocks:
Usage: Employed to specify initial conditions or setup during simulation, executing once at the beginning.
Example:
initial begin
// Initialization logic here
end
- Now let us see how these procedural statements work.
1] Blocking assignments:
- Syntax:
Specified using the ‘=’ operator. - Execution Flow:
Statements are executed sequentially in the order specified within the procedural block.
The execution of subsequent statements is blocked until the current assignment is completed. - Scope:
Blocking assignments within one procedural block do not impact the execution of statements in other procedural blocks. - Example:
Now let us consider below example to understand how blocking statements work. Below is not the complete verilog code but a module to understand the concept.
integer x,y,z;
initial
begin
x = 20;
y = 15;
z = 30;x = y + z;
y = x + 10;
z = x — y;
end
Now the output for above logic will be as follows:
initially, x=20,y=15,z=30
x becomes 45
y becomes 55
z becomes -10
- Initial Values:
Initially, the values of x, y, and z are set to 20, 15, and 30, respectively. - Execution Steps:
After the execution of the first statement (x = y + z), the value of x becomes 45.
The second statement (y = x + 10) utilizes the updated value of x (now 45), resulting in y becoming 55.
Finally, the third statement (z = x — y) uses the updated values of x (45) and y (55), causing z to become -10.
Provided below is the Verilog code for the logic mentioned above. Experiment with its implementation in simulation software to observe the output.
module blocking_assignment;
reg [31:0] x, y, z;initial begin
x = 20;
y = 15;
z = 30;// Blocking assignments
x = y + z; // x is assigned the value of y + z (15 + 30 = 45)
y = x + 10; // y is assigned the value of x + 10 (45 + 10 = 55)
z = x — y; // z is assigned the value of x — y (45–55 = -10)// Displaying the values after the assignments
$display(“x = %0d, y = %0d, z = %0d”, x, y, z);
end
endmodule
- Now let us consider the same example but with delays:
integer x,y,z;
initial
begin
x = 20;
y = 15;
z = 30;x = y + z;
#5 y = x + 10;
#10 z = x — y;
end
- Now the output for above logic will be as follows:
initially, x=20,y=15,z=30
x becomes 45
y becomes 55
z becomes -10
- Initial Values:
Initially, the values of x, y, and z are set to 20, 15, and 30, respectively. - Execution Steps:
After the execution of the first statement (x = y + z), the value of x becomes 45.
At time 0, the second statement (#5 y = x + 10) is scheduled to occur at time 5.
However, this scheduling doesn’t affect the immediate execution of the next statement.
At time 0, the third statement (#10 z = x — y) is scheduled to occur at time 10 + 5 = 15.
This means that the actual execution of the third statement occurs at time 15.
So, in the scenario with delays, the execution of the third statement (z = x — y) occurs at time 15, not immediately after the second statement. Therefore, the value of z becomes -10 at time 15.
2] Non Blocking Assignment:
- Syntax:
Specified using the ‘<=’ operator. - Key Characteristics:
Non-blocking assignments allow concurrent execution of statements within the same procedural block and do not block the execution of the next statement.
Particularly suitable for sequential logic implementation in Verilog, commonly used to model flip-flops and other sequential elements in digital circuits. - Sequential Logic Implementation:
Non-blocking assignments help avoid race conditions in sequential logic design.
When multiple signals are updated within the same clocked always block, non-blocking assignments ensure that all updates occur simultaneously at the next clock edge. - Example:
Let’s consider the same example used for blocking statements to illustrate how non-blocking statements work:
integer x, y, z;
initial begin
x = 20;
y = 15;
z = 30;x <= #10 y + z;
y <= #10 x + 10;
z <= #10 x — y;
end
- Output Explanation:
Initially, the values of x, y, and z are set to 20, 15, and 30.
After the execution of the statements at time 10 (due to delays), the values become:
x becomes 45
y becomes 30
z becomes -5 - Initially, the values of x, y, and z are set to 20, 15, and 30, respectively.
According to the given delay (#10), all statements within the initial block will execute at time 10 and will consider the initially defined values for calculation.
In conclusion, the significance of blocking and non-blocking assignments in Verilog coding cannot be overstated. These elements serve as the foundation for precise and effective digital circuit design, offering control over sequential and concurrent execution. As you venture further into the intricacies of Verilog, remember that mastering the art of assignments empowers you to create resilient and optimized digital systems. Happy coding!
