SIPO (Serial In Parallel Out):
- The Serial-In-Parallel-Out (SIPO) shift register facilitates serial input and generates a parallel output. Illustrated below is a 4-bit SIPO shift register utilizing D flip-flops, where each flip-flop is interconnected in a serial fashion and synchronized by identical clock signals. The output of one flip-flop is linked to the input of the subsequent flip-flop, forming a serial chain.
- Initially, all flip-flops are reset to Q3=Q2=Q1=Q0=0. Taking a 4-bit input data series, such as 1011, the first Least Significant Bit (LSB) bit (0) is considered as “Din” and is applied to the input of the initial flip-flop. Each flip-flop’s output is connected to a parallel output. The register’s stored word is updated with each falling edge of the clock signal, resulting in a parallel output.
- To commence, all flip-flops are set to a reset state: Q3 Q2 Q1 Q0 = 0000. Applying the first serial input bit (1) to the first flip-flop’s input, on the falling edge of the clock, the first flip-flop is triggered, latching the data. The shift register now holds Q3 Q2 Q1 Q0 = 1 0 0 0.
- Subsequently, applying the second serial input bit (1) to the first flip-flop’s input, the first flip-flop is triggered again on the falling edge of the clock, and the data is latched. The shift register now holds Q3 Q2 Q1 Q0 = 1 1 0 0.
- Continuing the process for the third and fourth serial input bits (0 and 1), after each clock edge, the shift register holds:
Clock Edge 3: Q3 Q2 Q1 Q0 = 0 1 1 0.
Clock Edge 4: Q3 Q2 Q1 Q0 = 1 0 1 1. - After all four clock edges, the final parallel output is Q3 Q2 Q1 Q0 = 1011. This iterative process ensures that the parallel output consistently represents the entire serial input data stream.
- SIPO shift registers find common application when there is a need to convert a serial data stream into a parallel format for subsequent processing in a digital system.
