Verilog Code for JK Flip Flop (With Explanation & Testbench) | #18

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a JK Flip-Flop in Verilog. The JK Flip-Flop is an advanced version of the SR Flip-Flop that eliminates the invalid state and provides more flexibility in sequential circuit design.

Depending on the inputs J and K, the output can set, reset, hold, or toggle, making it highly useful in counters and control circuits.

Below is the Verilog code for a JK Flip-Flop, implemented using a Behavioral Modeling approach:

📊 Block Diagram

In the behavioral modeling approach, we use conditional statements inside a clock-triggered block to define the flip-flop behavior.

module jk_flip_flop(input clk, input J, input K, output reg Q);

always @(posedge clk)
begin
  case ({J, K})
    2'b00: Q <= Q;     // No change
    2'b01: Q <= 1'b0;  // Reset
    2'b10: Q <= 1'b1;  // Set
    2'b11: Q <= ~Q;    // Toggle
  endcase
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, J, K;
  wire Q;
  
  jk_flip_flop jkff(clk, J, K, Q);
  
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end
  
  initial begin
    $monitor("At time %0t: J=%b K=%b Q=%b", $time, J, K, Q);
    
    J = 0; K = 0; #10;
    J = 0; K = 1; #10;
    J = 1; K = 0; #10;
    J = 1; K = 1; #10;
    J = 1; K = 1; #10;
    
    #10 $finish;
  end
endmodule

Explanation:

• When J = 0 and K = 0, the output remains unchanged.
• When J = 0 and K = 1, the flip-flop resets (Q = 0).
• When J = 1 and K = 0, the flip-flop sets (Q = 1).
• When J = 1 and K = 1, the output toggles.
• The always @(posedge clk) block ensures edge-triggered operation.

Conclusion

This Verilog implementation of a JK Flip-Flop demonstrates how multiple operations like set, reset, hold, and toggle can be achieved within a single sequential circuit. It is widely used in designing counters and control logic.

What’s Next?

Try implementing counters using JK Flip-Flops and observe state transitions. In the next post, we’ll explore more advanced sequential circuits and their Verilog implementations.

Happy Coding! 🚀