Step-by-step guide on how to design and implement a Half Adder using CMOS and sky130nm PDK.

• The purpose of this project is to design a CMOS Half ADDER using an Opensource EDA Tool called eSim, an Opensource Spice Simulator called ngspice, and Sky130 PDK.
• To explore the project, you can git clone using the command: git clone Github.

Table of Contents:

1. INTRODUCTION
2. INSTALLATION OF TOOLS
3. CIRCUIT DESIGN
   3.1 REFERENCE CIRCUIT DIAGRAM
   3.2 REFERENCE CIRCUIT WAVEFORM
4. IMPLEMENTATION
5. REFERENCE

1. INTRODUCTION

In this project, I am going to Design and Implement Half ADDER using CMOS Technology and I will also implement it using sky130nm technology. Design and Implementation will be done using esim and ngspice software. HALF Adder is the digital circuit that will add 2 inputs and give 2 outputs. 2 inputs are A, B and outputs are SUM, CARRY. Half Adder will do binary addition of A and B and will give the sum of 2 inputs at SUM output and carry bit at CARRY output. We can verify the output using Circuit Waveforms. This complete design and implementation is done using VLSI technology which has features such as high speed, low power, low cost, and small size.

2. INSTALLATION OF TOOLS

esim:

esim is an open-source EDA tool used for circuit design and simulation. Using esim we can draw a circuit using Kicad, generate netlist and simulate using Ngspice.

For more information: https://esim.fossee.in/home

Ngspice:

ngspice is the open-source spice simulator for electric and electronic circuits. We can design circuits using JFET, MOSFET, and passive elements like resistors, capacitors, etc.

For more information: http://ngspice.sourceforge.net

Sky130nm PDK:

The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit and related resources, which can be used to create manufacturable designs at SkyWater’s facility.

For more information: https://www.layouteditor.org/schematiceditor/libraries/skywater

The Download links for the above software are:

esim: https://esim.fossee.in/downloads

Ngspice: https://sourceforge.net/projects/ngspice/files/

Sky130 pdk: https://static.fossee.in/esim/installation-files/sky130_fd_pr.zip

Follow these steps for Sky130 download and implementaion:

1. Download sky130 from this link mentioned above and unzip it.
2. Save the .cir.out file in the sky_fd_pr folder as .cir file.
3. Open with notepad and add the path .lib “models/sky130.lib.spice” tt at the top.
4. Replace with CMOSP, mos_p with sky130_fd_pr_pfet_01v8 and CMOSN, mos_n with sky130_fd_pr_nfet_01v8.
5. To replace the inductor, capacitor, resistor do it this way, for Ex: L1 out gnd 1m by x1 out gnd mid 0 sky130_fd_pr__ind_03_90.

Note: For more details go to the cells folder in sky_fd_pr.

Open the specific component folder which you want to use.

Then open the test folder and check the SPICE file.

The SPICE file is an example of the implementation of that component.

You will get to know how to use the component in your ckt.

1. Now Run the circuit with ngspice.

To Run the ckt using ngspice:

1. Right-click on the .cir file.
2. Click on Open With.
3. Browse for the ngspice.
4. If ngspice is not present scroll down click on More Apps.
5. Go to the FOSSEE folder search for Ngspice and Run it.

3. CIRCUIT DESIGN

Half Adder is a digital circuit that will add 2 binary inputs and will give 2 outputs namely SUM and CARRY. The 2 inputs are A, B and outputs are SUM and CARRY. As we have 2 inputs we will have 4 input combinations. Using circuit design rules of CMOS we will design the circuit in such a way that the addition of 2 inputs will occur at SUM output and the carry bit will occur at CARRY output. While designing we have used a total of 16 Transistors. Half Adder using CMOS will be designed using 2 parts: PMOS (pull-up lattice) and NMOS (pull-down lattice). PMOS circuit is connected to supply voltage VDD and NMOS circuit is connected to ground GND. We will implement this circuit design using sky130nm technology. In the Circuit Waveform, we will verify the above implementation using clock pulse. In the output, we will give different input combinations through clock pulse and verify the logic using the output waveform.

3.1 REFERENCE CIRCUIT DIAGRAM

3.2 REFERENCE CIRCUIT WAVEFORM

4. IMPLEMENTATION

Now, we will design the complete circuit using our reference circuit diagram with PMOS logic above and NMOS logic below. After connecting the complete we will get a circuit like below:

Label each and every component and port and check electrical rule checking and generate netlist file using spice and make changes in the netlist to add sky130 models. The netlist generated initially is as shown below:

C:\SPB_Data\eSim-Workspace\Half_Adder\abc.cir
EESchema Netlist Version 1.1 (Spice format) creation date: 2/14/2022 7:54:22 PM
To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to N
To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
Sheet Name: /
M7 Net-M10-Pad3 /A /VDD /VDD mosfet_p
M9 Net-M10-Pad3 /B /VDD /VDD mosfet_p
M8 /SUM /A0 Net-M10-Pad3 /VDD mosfet_p
M10 /SUM /B0 Net-M10-Pad3 /VDD mosfet_p
M5 /SUM /A Net-M5-Pad3 GND mosfet_n
M11 /SUM /A0 Net-M11-Pad3 GND mosfet_n
M12 Net-M11-Pad3 /B0 GND GND mosfet_n
M6 Net-M5-Pad3 /B GND GND mosfet_n
M13 /CARRY /A0 GND GND mosfet_n
M16 /CARRY /B0 GND GND mosfet_n
M14 Net-M14-Pad1 /A0 /VDD /VDD mosfet_p
M15 /CARRY /B0 Net-M14-Pad1 /VDD mosfet_p
M3 /A0 /A /VDD /VDD mosfet_p
M1 /A0 /A GND GND mosfet_n
M4 /VDD /B /B0 /VDD mosfet_p
M2 /B0 /B GND GND mosfet_n
U1 /A /B /VDD /SUM /CARRY PORT
.end

The netlist after making sky130 models syntax changes is as shown below:

c:\spb_data\esim-workspace\half_adder\half_adder.cir
.lib “sky130_fd_pr/models/sky130.lib.spice” tt
xm7 net-m10-pad3 a vdd vdd sky130_fd_pr__pfet_01v8 w=1 l=0.5
xm9 net-m10-pad3 b vdd vdd sky130_fd_pr__pfet_01v8 w=1 l=0.5
xm8 sum a0 net-m10-pad3 vdd sky130_fd_pr__pfet_01v8 w=1 l=0.5
xm10 sum b0 net-m10-pad3 vdd sky130_fd_pr__pfet_01v8 w=1 l=0.5
xm5 sum a net-m5-pad3 gnd sky130_fd_pr__nfet_01v8 w=0.42 l=0.5
xm11 sum a0 net-m11-pad3 gnd sky130_fd_pr__nfet_01v8 w=0.42 l=0.5
xm12 net-m11-pad3 b0 gnd gnd sky130_fd_pr__nfet_01v8 w=0.42 l=0.5
xm6 net-m5-pad3 b gnd gnd sky130_fd_pr__nfet_01v8 w=0.42 l=0.5
xm13 carry a0 gnd gnd sky130_fd_pr__nfet_01v8 w=0.42 l=0.5
xm16 carry b0 gnd gnd sky130_fd_pr__nfet_01v8 w=0.42 l=0.5
xm14 net-m14-pad1 a0 vdd vdd sky130_fd_pr__pfet_01v8 w=1 l=0.5
xm15 carry b0 net-m14-pad1 vdd sky130_fd_pr__pfet_01v8 w=1 l=0.5
xm3 a0 a vdd vdd sky130_fd_pr__pfet_01v8 w=1 l=0.5
xm1 a0 a gnd gnd sky130_fd_pr__nfet_01v8 w=0.42 l=0.5
xm4 vdd b b0 vdd sky130_fd_pr__pfet_01v8 w=1 l=0.5
xm2 b0 b gnd gnd sky130_fd_pr__nfet_01v8 w=0.42 l=0.5
Vdd vdd 0 3.3
Vd0 a 0 pulse(0 2.2 0us 0s 0s 20us 40us)
Vd1 b 0 pulse(0 2.2 0us 0s 0s 10us 20us)
u1 /a /b /vdd /sum /carry port
.tran 0.1us 60us
Control Statements
.control
run
plot V(carry) V(sum) +4 V(b) +12 V(a)+15
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end

Note: sky130_fr_pd file for sky130 model must be present on the same file as .cir.out.

Truth Table for Half Adder using CMOS is as shown below:

Now, run the .cir.out file using ngspice and we will get the circuit waveforms as follows:

From the above waveform, we can verify the truth table for Half Adder using CMOS.

5. REFERENCES:

[1]N. Zhuang and H. Wu, “A new design of the CMOS full adder,” IEEE Journal of Solid-State Circuits, vol. 27, №5, pp. 840–844, May 1992.

[2]N. H. E. Weste and K. Eshraghian, “Principles of CMOS VLSI design,” Addison Wesley, 1993.

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