DYNAMIC CMOS

 - Dynamic CMOS basically relies on temporarily storing signals using various load capacitances.

- The below diagram shows the Basic diagram of Dynamic CMOS:

- Here we have a PMOS circuit connected to the Vdd supply and a clock applied to its gate terminal. Then we have a Pull Down Network made of an NMOS which has k no. of inputs implementing a Boolean equation. Then we have an NMOS circuit connected to the ground and clock signal connected at its gate terminal. Output is taken between the PMOS and Pull-down network. Here we have also connected a load capacitance.

- Here we can observe that we use only a single PMOS and (k+1) NMOS is used. Whereas in static CMOS k number of PMOS and k number of NMOS are used. Hence its size will be less compared to static CMOS. It also has less capacitive loading and higher switching speed as compared to Static CMOS.

— Working :

Consider, the below circuit diagram for understanding the working of dynamic CMOS.

Here, instead of a pull-down network of NMOS consider a single NMOS. Dynamic CMOS operates in 2 modes:
1] Pre-charging mode.
2] Evaluation mode.

Let us understand these two operating modes of Dynamic CMOS based on a timing diagram shown below:

1] Here, we can observe 3 waveforms: clk, input, and output based on time t.
2] Based on the clock and input waveform we can observe the output waveform.
3] CASE 1: When clock = 0 and input =1 then according to the functionality of NMOS and PMOS, PMOS will be in ON state, the Pull down network NMOS will be in ON state and lower NMOS will be in OFF state. Hence, the load capacitance CL will get charged via PMOS by voltage Vdd which is referred to as the Pre-charging mode.
4] CASE 2: When clock = 1 and input =1 then according to the functionality of NMOS and PMOS, PMOS will be in OFF state, the Pull down network NMOS will be in ON state and lower NMOS will be in ON state. Hence, the load capacitance CL will get Discharged via NMOS and get grounded. This discharging is based on total resistance in the circuit. So ideally, the output will be logic 0 after case 2. Here you can observe that input is given as logic 1 and output is 0, hence during case 2 Dynamic CMOS acts as an Inverter.
5] CASE 3: When clock = 0 and input =0 then according to the functionality of NMOS and PMOS, PMOS will be in ON state, the Pull down network NMOS will be in OFF state and lower NMOS will be in OFF state. Hence, the load capacitance CL will get charged via PMOS by voltage Vdd. This is also called Pre-charging mode.
6] CASE 4: Now, when clock = 1 and Input = 0, according to the functionality of NMOS and PMOS, PMOS will be in OFF state, the Pull-down network NMOS will be in OFF state and lower NMOS will be in ON state. Here, the load capacitance doesn’t find a path to get discharged so it will maintain its state Vdd only. Input will act as an open circuit i.e., high impedance state, and output will be Vdd or ideally logic 1.

So, pre-charging be done when the clock is 0 which is case 1 and case 3 and Evaluation will be done when the clock is 1 where, Dynamic CMOS will act as Inverter i.e., in case 2 and case 4.

— Along with a few advantages such as less number of transistors, small size, and high switching speed Dynamic CMOS also has some disadvantages as follows:

1] It continuously needs clock input for proper functioning.
2] As this circuit has to be pre-charged after every evaluation, some excess power is consumed.
3] For the complete pre-charging mode, the output must be equal to Vdd. Now, if the clock input takes a longer time to arrive or the PDN circuit takes a longer time to evaluate its output then the next block will start evaluating with incorrect input values. Hence, to solve this we need to use an additional block of inverter or domino block so the next bloc is not evaluated till the previous output has been evaluated.

In this way, the Dynamic CMOS will function in two modes, pre-charging, and Evaluation mode.

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