Step-by-step guide on how to design and implement Counters with testbench code on Xilinx Vivado design tool using Verilog HDL.

In this project we will see how to implement all Counters with testbench code on Xilinx Vivado design tool.

Step 1: Click on New Project -> Next

Step 2: Enter Project Name and Select appropriate Project Location -> Next

Step 3: Select RTL Project -> Next

Step 4: Click on Create File and create file with file name up_counter -> Next

Step 5: We will not add the Constraint file So click on Next

Step 6: For Default Part click on Next as we are not using any development Board

Step 7: Check the New Project Summary and click on Finish.

Step 8: Now you will be prompted with the Define module page but we will create the complete code from scratch so click on cancel and Yes

Step 9: Now on the Home Page click on Sources -> Design Sources -> Non-module Files

Step 10: Enter the below codes in the “up_counter.v” files.

module up_counter(clk, reset, counter);

input clk, reset;
output[3:0] counter;
reg[3:0] count;

always @(posedge clk or posedge reset)
begin
if(reset)
count<=4'd15;
else
count<=count-4'd1;
end
assign counter = count;
endmodule

Step 11: Now to write the testbench code for and gate right click on Design Sources -> Add Sources -> Add or create design sources -> Create File -> Add File name as tb_up_counter -> Finish -> Ok -> Yes

Step 12: Now open the testbench file and enter the below testbench code

module tb_up_counter();

reg clk, reset;
wire[3:0] counter;

up_counter uut(clk,reset,counter);

initial begin
$display(“Testing UP Counter”);
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;

end
endmodule

Here, in testbench code we do not define values in entity hence we have kept it empty. Then in architecture we have copied the components of up_counter and defined signals for connecting the ports of counter. Inside the process statement we write all test cases and define the respective delays.

Step 13: Now as we have written all the codes let’s launch the simulation. Enter launch_simulation in the Tcl Console and press Enter.

We have successfully implemented up counter with testbench code. Click on Zoom Fit to see the output waveform more clearly and verify the outputs.

If you want to implement other counters the process would be same except the Verilog codes. Visit below links to see how to implement other Counters:

1] Down Counter
2] Up Down Counter

In this way, we can implement Counters using testbench codes.

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