Verilog Down Counter

 down_counter.v

module down_counter(clk, reset, counter);

input clk, reset;
output[3:0] counter;
reg[3:0] count;

always @(posedge clk or posedge reset)
begin
if(reset)
count<=4'd15;
else
count<=count-4'd1;
end
assign counter = count;
endmodule

tb_down_counter.v

module tb_down_counter();

reg clk, reset;
wire[3:0] counter;

down_counter uut(clk,reset,counter);

initial begin
$display(“Testing DOWN Counter”);
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;

end
endmodule