Step-by-step guide on how to design and implement Flip Flops with testbench code on Xilinx Vivado design tool.

 In this project we will see how to implement all flip flops with testbench code on Xilinx Vivado design tool. Below diagram shows all flip flops along with there truth tables. To learn about how flip flops work in detail visit my blog: Diving into Sequential Circuits: Part 2 - Flip Flops 

Step 1: Click on New Project -> Next

Step 2: Enter Project Name and Select appropriate Project Location -> Next

Step 3: Select RTL Project -> Next

Step 4: Click on Create File and create file with file name d_flip_flop -> Next

Step 5: We will not add the Constraint file So click on Next

Step 6: For Default Part click on Next as we are not using any development Board

Step 7: Check the New Project Summary and click on Finish

Step 8: Now you will be prompted with the Define module page but we will create the complete code from scratch so click on cancel and Yes

Step 9: Now on the Home Page click on Sources -> Design Sources -> Non-module Files

Step 10: Enter the below codes in the “d_flip_flop.vhd” files

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d_flip_flop is
Port ( D, CLK : in STD_LOGIC;
Q, Qb : out STD_LOGIC);
end d_flip_flop;

architecture Behavioral of d_flip_flop is

begin
process (D, CLK)
begin

if (rising_edge(CLK)) then
Q <= D;
Qb <= not D;

end if;
end process;
end Behavioral;

Step 11: Now to write the testbench code for and gate right click on Design Sources -> Add Sources -> Add or create design sources -> Create File -> Add File name as tb_d_flip_flop -> Finish -> Ok -> Yes

Step 12: Now open the testbench file and enter the below testbench code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tb_d_flip_flop is
end entity;

architecture Behavioural of tb_d_flip_flop is

component d_flip_flop is
Port ( D, CLK: in STD_LOGIC;
Q, Qb : out STD_LOGIC);
end component ;

signal D, CLK, Q, Qb : STD_LOGIC;

begin
uut: d_flip_flop port map(
D => D,
CLK => CLK,
Q => Q,
Qb => Qb);

Clock : process
begin
CLK <= ‘1’;
wait for 10 ns;
CLK <= ‘0’;
wait for 10 ns;
end process;

stim : process
begin

D <= ‘0’;
wait for 40 ns;
D <= ‘1’;
wait for 40 ns;

end process;
end Behavioural;

Here, in testbench code we do not define values in entity hence we have kept it empty. Then in architecture we have copied the components of d_flip_flop and defined signals for connecting the ports of flip flop. Inside the process statement we write all 2 test cases from truth table and define the respective delays.

Step 13: Now as we have written all the codes let’s launch the simulation. Enter launch_simulation in the Tcl Console and press Enter

We have successfully implemented d flip flop with testbench code. Click on Zoom Fit to see the output waveform more clearly and verify the outputs.

If you want to implement other Flip Flops then the process would be same except the VHDL codes. Visit below links to see how to implement other Flip Flops: 

1] SR Flip Flop

2] JK Flip Flop

3] T Flip Flop

In this way, we can implement all Flip Flops using testbench codes.

Like, Share, and Follow me if you like my content.
Thank You