SR Flip Flop

 sr_flip_flop.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sr_flip_flop is
Port ( S, R, CLK : in STD_LOGIC;
Q, Qb : out STD_LOGIC);
end sr_flip_flop;

architecture Behavioral of sr_flip_flop is

begin
process (S, R, CLK)
variable temp: std_logic;
begin

if (rising_edge(CLK)) then
if(S=’0' and R=’0')then
temp:=temp;
elsif(S=’0' and R=’1')then
temp:=’0';
elsif(S=’1' and R=’0')then
temp:=’1';
elsif(S=’1' and R=’1')then
temp:=’Z’;
end if;
end if;
Q<=temp;
Qb<= not temp;

end process;
end Behavioral;

tb_sr_flip_flop.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tb_sr_flip_flop is
end entity;

architecture Behavioural of tb_sr_flip_flop is

component sr_flip_flop is
Port ( S, R, CLK: in STD_LOGIC;
Q, Qb : out STD_LOGIC);
end component ;

signal S, R, CLK, Q, Qb : STD_LOGIC;

begin
uut: sr_flip_flop port map(
S => S,
R => R,
CLK => CLK,
Q => Q,
Qb => Qb);

Clock : process
begin
CLK <= ‘1’;
wait for 10 ns;
CLK <= ‘0’;
wait for 10 ns;
end process;

stim : process
begin

S <= ‘0’ ; R<=’0';
wait for 20 ns;
S <= ‘0’ ; R<=’1';
wait for 20 ns;
S <= ‘1’ ; R<=’0';
wait for 20 ns;
S <= ‘1’ ; R<=’1';
wait for 20 ns;
end process;
end Behavioural;

The output waveform for SR Flip Flop will be as follows: