VHDL - Not Gate

 not_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity not_gate is
Port (
a: in std_logic;
c: out std_logic);
end not_gate;

architecture Behavioral of not_gate is
begin
c<= not a;
end Behavioral;

tb_not_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_not_gate is
end tb_not_gate;

architecture Behavioral of tb_not_gate is
component not_gate is
Port(a: in std_logic;
c: out std_logic);
end component;
signal tb_a,tb_c : std_logic:=’0';

begin
uut : not_gate port map(
a=>tb_a, c=>tb_c
);

stim_process: process
begin

tb_a<=’0' ; wait for 100ns;
tb_a<=’1' ; wait for 100ns;

end process;
end Behavioral;

The output waveform for not gate will be as follows: