T Flip Flop

 t_flip_flop.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity t_flip_flop is
Port ( T, CLK : in STD_LOGIC;
Q, Qb : out STD_LOGIC);
end t_flip_flop;

architecture Behavioral of t_flip_flop is
begin
process (T, CLK)
variable temp: std_logic:=’0';
begin

if (rising_edge(CLK)) then
if(T=’1')then
temp:=not temp;
end if;

Q<=temp;
Qb<= not temp;

end if;
end process;
end Behavioral;

tb_t_flip_flop.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tb_t_flip_flop is
end entity;

architecture Behavioural of tb_t_flip_flop is

component t_flip_flop is
Port ( T, CLK: in STD_LOGIC;
Q, Qb : out STD_LOGIC);
end component ;

signal T, CLK, Q, Qb : STD_LOGIC;

begin
uut: t_flip_flop port map(
T => T,
CLK => CLK,
Q => Q,
Qb => Qb);

Clock : process
begin
CLK <= ‘1’;
wait for 10 ns;
CLK <= ‘0’;
wait for 10 ns;
end process;

stim : process
begin

T <= ‘0’ ;
wait for 20 ns;
T <= ‘1’ ;
wait for 20 ns;
end process;
end Behavioural;

The output waveform for T Flip Flop will be as follows: