Step-by-step guide on how to design and implement a Full Adder using Half Adder with Xilinx Vivado design tool.

Full Adder is a combinational logic circuit that adds three inputs and produces two outputs. The diagram below illustrates the basic block diagram and circuit diagram of a Full Adder, where A, B, and C_in are the inputs, and Sum and C_out are the outputs. Here, C_in is commonly referred to as the carry input, and C_out is known as the carry output.

The table below presents the truth table of a Full Adder.

From the input, we can observe that the sum output is high only when at least one input is equal to 1 or when all inputs are equal to 1. C_out is equal to 1 when two or three inputs are equal to 1. The output equations of a Full Adder are as follows:

If we want to design the Full Adder using half adders, the circuit diagram and block diagram for it will be as follows:

Therefore, we need two Half Adders and one OR gate to design a Full Adder.

In this project, we will design and implement the Full Adder using Half Adders with the Xilinx Vivado design tool.

Step 1: Click on New Project -> Next

Step 2: Enter Project Name and Select appropriate Project Location -> Next

Step 3: Select RTL Project -> Next

Step 4: Click on Create File and create 3 files with file names or_gate, half_adder and full_adder -> Next

Step 5: We will not add the Constraint file So click on Next

Step 6: For Default Part click on Next as we are not using any development Board

Step 7: Check the New Project Summary and click on Finish

Step 8: Now you will be prompted with the Define module page but we will create the complete code from scratch so click on cancel and Yes

Step 9: Now on the Home Page click on Sources -> Design Sources -> Non-module Files

Step 10: Enter the below codes in the “.vhd” files

or_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or_gate is
Port ( and_a : in STD_LOGIC;
and_b : in STD_LOGIC;
and_c : out STD_LOGIC);
end or_gate;

architecture Behavioral of or_gate is
begin
and_c<= and_a or and_b;
end Behavioral;

half_adder.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder is
Port ( half_adder_a : in STD_LOGIC;
half_adder_b : in STD_LOGIC;
half_adder_sum : out STD_LOGIC;
half_adder_carry : out STD_LOGIC);
end half_adder;

architecture Behavioral of half_adder is
begin
half_adder_sum <= half_adder_a xor half_adder_b;
half_adder_carry <= half_adder_a and half_adder_b;
end Behavioral;

full_adder.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
Port ( full_adder_a : in STD_LOGIC;
full_adder_b : in STD_LOGIC;
full_adder_c : in std_logic;
full_adder_sum : out STD_LOGIC;
full_adder_carry : out STD_LOGIC);
end full_adder;

architecture Behavioral of full_adder is

component half_adder is
port(half_adder_a : in STD_LOGIC;
half_adder_b : in STD_LOGIC;
half_adder_sum : out STD_LOGIC;
half_adder_carry : out STD_LOGIC
);
end component;

component or_gate is port(
and_a : in STD_LOGIC;
and_b : in STD_LOGIC;
and_c : out STD_LOGIC
);
end component;
signal s1,s2,s3: std_logic;

begin
lab1: half_adder port map(half_adder_a=> full_adder_a, half_adder_b=>full_adder_b, half_adder_sum=> s1, half_adder_carry=>s2);
lab2: half_adder port map(half_adder_a=> s1, half_adder_b=>full_adder_c, half_adder_sum=> full_adder_sum, half_adder_carry=>s3);
lab3: or_gate port map(and_a=> s2, and_b=>s3, and_c=> full_adder_carry);
end Behavioral;

Here, we have written vhdl code for or gate and half adder using Dataflow modelling and for full adder using Structural modelling.

Step 11: Now to write the testbench code for above design right click on Design Sources -> Add Sources -> Add or create design sources -> Create File -> Add File name as tb_full_adder -> Finish -> Ok -> Yes

Step 12: Now open the testbench file and enter the below testbench code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_full_adder is
— Port ( );
end tb_full_adder;

architecture Behavioral of tb_full_adder is
component full_adder is port(
full_adder_a : in STD_LOGIC;
full_adder_b : in STD_LOGIC;
full_adder_c : in std_logic;
full_adder_sum : out STD_LOGIC;
full_adder_carry : out STD_LOGIC

);
end component;

signal a, b, c ,sum, carry: std_logic:=’0';
begin

uut: full_adder port map(

full_adder_a=>a,
full_adder_b=>b,
full_adder_c=>c,
full_adder_sum=>sum,
full_adder_carry=>carry
);

stim_proc: process

begin
a<=’0' ; b<=’0'; c<=’0'; wait for 100ns;
a<=’0' ; b<=’0'; c<=’1'; wait for 100ns;
a<=’0' ; b<=’1'; c<=’0'; wait for 100ns;
a<=’0' ; b<=’1'; c<=’1'; wait for 100ns;
a<=’1' ; b<=’0'; c<=’0'; wait for 100ns;
a<=’1' ; b<=’0'; c<=’1'; wait for 100ns;
a<=’1' ; b<=’1'; c<=’0'; wait for 100ns;
a<=’1' ; b<=’1'; c<=’1'; wait for 100ns;

end process;
end Behavioral;

Here, in testbench code we do not define values in entity hence we have kept it empty. Then in architecture we have copied the components of full_adder and defined signals for connecting the ports of full adder. Inside the process statement we write all 8 test cases from truth table and define the delay as 100ns.

Step 13: Now as we have written all the codes let’s launch the simulation. Enter launch_simulation in the Tcl Console and press Enter

We have successfully implemented full adder using half adder with testbench code. Click on Zoom Fit to see the output waveform more clearly and verify the outputs.

Like, Share, and Follow me if you like my content.
Thank You