VHDL - Or Gate

 or_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or_gate is
Port (
a: in std_logic;
b: in std_logic;
c: out std_logic);
end or_gate;

architecture Behavioral of or_gate is
begin
c<= a or b;
end Behavioral;

tb_or_gate.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_or_gate is
end tb_or_gate;

architecture Behavioral of tb_or_gate is
component or_gate is
Port(a: in std_logic;
b: in std_logic;
c: out std_logic);
end component;
signal tb_a,tb_b,tb_c : std_logic:=’0';

begin
uut : or_gate port map(
a=>tb_a, b=>tb_b, c=>tb_c
);

stim_process: process
begin

tb_a<=’0' ; tb_b<=’0'; wait for 100ns;
tb_a<=’0' ; tb_b<=’1'; wait for 100ns;
tb_a<=’1' ; tb_b<=’0'; wait for 100ns;
tb_a<=’1' ; tb_b<=’1'; wait for 100ns;

end process;
end Behavioral;

The output waveform for or gate will be as follows: