Mastering Verilog: Implementing a SR Flip Flop

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of an SR Flip-Flop in Verilog. The SR (Set-Reset) Flip-Flop is one of the simplest sequential circuits used to store a single bit of data.

It has two inputs, S (Set) and R (Reset), which control the output state. This flip-flop forms the basic foundation for more advanced flip-flops like JK and D Flip-Flops.

Below is the Verilog code for an SR Flip-Flop, implemented using a Behavioral Modeling approach:

📊 Block Diagram

In the behavioral modeling approach, we use conditional logic inside a clock-triggered block to define the output behavior.

module sr_flip_flop(input clk, input S, input R, output reg Q);

always @(posedge clk)
begin
  case ({S, R})
    2'b00: Q <= Q;     // Hold
    2'b01: Q <= 1'b0;  // Reset
    2'b10: Q <= 1'b1;  // Set
    2'b11: Q <= 1'bx;  // Invalid state
  endcase
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, S, R;
  wire Q;
  
  sr_flip_flop srff(clk, S, R, Q);
  
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end
  
  initial begin
    $monitor("At time %0t: S=%b R=%b Q=%b", $time, S, R, Q);
    
    S = 0; R = 0; #10;
    S = 1; R = 0; #10;
    S = 0; R = 1; #10;
    S = 1; R = 1; #10;
    
    #10 $finish;
  end
endmodule

Explanation:

• When S = 0 and R = 0, the output remains unchanged (hold condition).
• When S = 1 and R = 0, the flip-flop sets (Q = 1).
• When S = 0 and R = 1, the flip-flop resets (Q = 0).
• When S = 1 and R = 1, it results in an invalid state.
• The always @(posedge clk) block ensures edge-triggered operation.

Conclusion

This Verilog implementation of an SR Flip-Flop demonstrates the basic storage mechanism in sequential circuits. While simple, it highlights the importance of avoiding invalid input conditions in digital design.

What’s Next?

Now that you’ve explored SR, D, JK, and T Flip-Flops, try comparing their behavior and applications. In the next post, we’ll move toward registers and counters.

Happy Coding! 🚀