Mastering Verilog: Implementing a T Flip Flop

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a T Flip-Flop in Verilog. A T Flip-Flop (Toggle Flip-Flop) is a sequential circuit that changes its state whenever the input T is high and a clock edge occurs.

It is commonly used in counters and frequency division circuits, where toggling behavior is required.

Below is the Verilog code for a T Flip-Flop, implemented using a Behavioral Modeling approach:

📊 Block Diagram

In the behavioral modeling approach, we use clock-triggered logic to toggle the output based on the input condition.

module t_flip_flop(input clk, input T, output reg Q);

always @(posedge clk)
begin
  if (T)
    Q <= ~Q;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, T;
  wire Q;
  
  t_flip_flop tff(clk, T, Q);
  
  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end
  
  initial begin
    $monitor("At time %0t: T=%b Q=%b", $time, T, Q);
    
    T = 0; #10;
    T = 1; #10;
    T = 1; #10;
    T = 0; #10;
    
    #10 $finish;
  end
endmodule

Explanation:

• The T Flip-Flop toggles its output when T = 1 at the rising edge of the clock.
• If T = 0, the output remains unchanged.
• The always @(posedge clk) block ensures edge-triggered behavior.
• Non-blocking assignment (<=) is used for sequential logic.
• The testbench verifies the toggling behavior under different input conditions.

Conclusion

This Verilog implementation of a T Flip-Flop demonstrates how toggling behavior can be achieved using sequential logic. It is widely used in designing counters and frequency dividers in digital systems.

What’s Next?

Try implementing a JK Flip-Flop or counters using this T Flip-Flop. In the next post, we’ll explore more sequential circuits and their Verilog implementations.

Happy Coding! 🚀