Verilog Code for 4-bit Down Counter (With Explanation & Testbench) | #23

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Down Counter in Verilog. A down counter is a sequential circuit that decrements its output value by one on every clock cycle.

It is commonly used in digital systems for countdown operations, timers, and control logic.

Below is the Verilog code for a 4-bit Down Counter, implemented using a Behavioral Modeling approach:

In this design, the counter decreases its value by one at each rising edge of the clock signal.

module down_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b1111;
  else
    Q <= Q - 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  down_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%b", $time, Q);

    reset = 1; #10;
    reset = 0;

    #100 $finish;
  end
endmodule

Explanation:

• The counter decrements its value by 1 on every rising edge of the clock.
• The reset signal initializes the counter to the maximum value (1111).
• The output Q represents the current count value.
• The counter operates synchronously with the clock signal.
• After reaching the minimum value (0000), it wraps around to 1111.

Conclusion

This Verilog implementation of a Down Counter demonstrates how countdown operations can be implemented using sequential logic. It is widely used in timers and control circuits.

What’s Next?

Try implementing an Up-Down Counter to combine both incrementing and decrementing operations in a single design. In the next post, we’ll explore more advanced counter techniques.

Happy Coding! 🚀