Verilog Code for Mod-N Counter (Mod-10 Example) (With Explanation & Testbench) | #25

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Mod-N Counter in Verilog. A Mod-N counter is a counter that counts from 0 up to (N-1) and then resets back to 0.

This type of counter is widely used in digital systems where a specific counting range is required, such as timers and frequency dividers.

Below is the Verilog code for a Mod-10 Counter, implemented using a Behavioral Modeling approach:

module mod_n_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

parameter N = 10;

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else if (Q == N-1)
    Q <= 4'b0000;
  else
    Q <= Q + 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  mod_n_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%d", $time, Q);

    reset = 1; #10;
    reset = 0;

    #150 $finish;
  end
endmodule

Explanation:

• The counter increments on each rising edge of the clock.
• When the count reaches N-1, it resets back to zero.
• The parameter N defines the modulus of the counter.
• The reset signal initializes the counter to zero.
• This design is flexible and can be modified for any value of N.

Conclusion

This Verilog implementation of a Mod-N Counter demonstrates how controlled counting ranges can be achieved using simple logic. It is widely used in timing circuits and digital applications requiring specific count limits.

What’s Next?

Try implementing Ring Counters and Johnson Counters to explore more advanced counter designs. In the next post, we’ll continue building on sequential logic concepts.

Happy Coding! 🚀