Verilog Code for 4-bit Up Counter (With Explanation & Testbench) | #22

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of an Up Counter in Verilog. An up counter is a sequential circuit that increments its output value by one on every clock cycle.

It is widely used in digital systems for counting operations, timing applications, and frequency division.

Below is the Verilog code for a 4-bit Up Counter, implemented using a Behavioral Modeling approach:

In this design, the counter increases its value by one at each rising edge of the clock signal.

module up_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else
    Q <= Q + 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  up_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%b", $time, Q);

    reset = 1; #10;
    reset = 0;

    #100 $finish;
  end
endmodule

Explanation:

• The counter increments its value by 1 on every rising edge of the clock.
• The reset signal initializes the counter to zero.
• The output Q represents the current count value.
• The counter operates synchronously with the clock signal.
• After reaching the maximum value (1111), it wraps around to 0000.

Conclusion

This Verilog implementation of an Up Counter demonstrates a basic counting mechanism using sequential logic. It is widely used in digital systems for timing, sequencing, and control applications.

What’s Next?

Try implementing a Down Counter or Up-Down Counter to explore more flexible counting operations. In the next post, we’ll continue building advanced counter designs.

Happy Coding! 🚀