Verilog Code for Synchronous Counter (With Explanation & Testbench) | #21

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Synchronous Counter in Verilog. A synchronous counter is a sequential circuit where all flip-flops are driven by the same clock signal.

Unlike asynchronous counters, all bits in a synchronous counter change simultaneously on the clock edge, making it faster and more reliable for high-speed applications.

Below is the Verilog code for a 4-bit Synchronous Counter, implemented using a Behavioral Modeling approach:

In the behavioral modeling approach, all bits are updated together using a single clock signal.

module sync_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else
    Q <= Q + 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  sync_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%b", $time, Q);

    reset = 1; #10;
    reset = 0;

    #100 $finish;
  end
endmodule

Explanation:

• The counter increments its value on each rising edge of the clock.
• The reset signal initializes the counter to zero.
• All flip-flops are triggered by the same clock signal.
• This ensures all bits change simultaneously, reducing delay.
• The output Q represents the current count value.

Conclusion

This Verilog implementation of a Synchronous Counter demonstrates a faster and more efficient counting mechanism compared to asynchronous counters. It is widely used in high-speed digital systems.

What’s Next?

Try implementing an Up-Down Counter or Mod-N Counter to explore more advanced counter designs. In the next post, we’ll continue building on sequential logic concepts.

Happy Coding! 🚀