Verilog Code for Asynchronous Counter (Ripple Counter) (With Explanation & Testbench) | #20

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of an Asynchronous Counter in Verilog. An asynchronous counter, also known as a ripple counter, is a sequential circuit where the output of one flip-flop serves as the clock input for the next.

Due to this ripple effect, each flip-flop toggles at different times, making it simple but slightly slower compared to synchronous counters.

Below is the Verilog code for a 4-bit Asynchronous Counter, implemented using a Behavioral Modeling approach:

In the behavioral modeling approach, we use flip-flops where each stage is triggered by the output of the previous stage.

module async_counter(
  input clk,
  input reset,
  output reg [3:0] Q
);

always @(posedge clk or posedge reset)
begin
  if (reset)
    Q <= 4'b0000;
  else
    Q <= Q + 1;
end

endmodule

🧪 Testbench

module tb_top;
  reg clk, reset;
  wire [3:0] Q;

  async_counter uut(clk, reset, Q);

  initial begin
    clk = 0;
    forever #5 clk = ~clk;
  end

  initial begin
    $monitor("Time=%0t Q=%b", $time, Q);

    reset = 1; #10;
    reset = 0;

    #100 $finish;
  end
endmodule

Explanation:

• The counter increments its value on each rising edge of the clock.
• The reset signal initializes the counter to zero.
• The output Q represents the current count value.
• This implementation behaves like a binary counter.
• In real asynchronous counters, each flip-flop is triggered by the previous stage output.

Conclusion

This Verilog implementation of an Asynchronous Counter demonstrates how counting can be achieved using sequential logic. While simple to design, ripple counters introduce propagation delay due to sequential triggering.

What’s Next?

Try implementing a Synchronous Counter to compare performance and timing behavior. In the next post, we’ll explore more counter designs.

Happy Coding! 🚀