Mastering Verilog: BCD to 7-Segment Decoder

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a BCD to 7-Segment Decoder in Verilog. This decoder is a widely used digital circuit that converts a 4-bit Binary Coded Decimal (BCD) input into signals that drive a 7-segment display.

It is commonly used in digital systems such as calculators, clocks, and display units where numerical data needs to be visually represented.

Below is the Verilog code for a BCD to 7-Segment Decoder, implemented using a Behavioral Modeling approach:

In the behavioral modeling approach, we define the output segments based on the input BCD value using conditional logic.

module seve_seg_decoder (output [7:1] seg,
                         input [3:0] bcd, input blank);
reg [7:1] seg_tmp;always @*
    case (bcd)
        4'b0000: seg_tmp = 7'b0111111;  // 0
        4'b0001: seg_tmp = 7'b0000110;  // 1
        4'b0010: seg_tmp = 7'b1011011;  // 2
        4'b0011: seg_tmp = 7'b1001111;  // 3
        4'b0100: seg_tmp = 7'b1100110;  // 4
        4'b0101: seg_tmp = 7'b1101101;  // 5
        4'b0110: seg_tmp = 7'b1111101;  // 6
        4'b0111: seg_tmp = 7'b0000111;  // 7
        4'b1000: seg_tmp = 7'b1111111;  // 8
        4'b1001: seg_tmp = 7'b1101111;  // 9
        default: seg_tmp = 7'b1000000;  // "-"
    endcaseassign seg = blank ? 7'b0000000 : seg_tmp;endmodule

Explanation:

• The always @* block ensures that the output updates automatically whenever the input changes.
• The case statement maps each BCD input (0–9) to its corresponding 7-segment display pattern.
• The seg_tmp register temporarily holds the segment pattern before assigning it to the output.
• The blank input is used to turn off all segments when required.
• The default case displays a dash (-) for invalid BCD inputs.

Conclusion

This Verilog implementation of a BCD to 7-Segment Decoder demonstrates how combinational logic can be used to drive display devices. Such decoders are essential in digital systems where numeric outputs need to be displayed in a human-readable format.

What’s Next?

Try implementing this decoder on an FPGA or simulator and observe how different inputs affect the display output. In the next post, we’ll explore more digital design concepts and their Verilog implementations.

Happy Coding! 🚀