Mastering Verilog: Implementing a 4-Bit Full Adder

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a 4-bit Full Adder in Verilog. A full adder is a fundamental digital circuit used to perform binary addition, and by combining multiple 1-bit full adders, we can build multi-bit adders.

This design follows a ripple carry architecture, where the carry output from each stage is passed to the next stage.

Below is the Verilog code for a 4-bit Full Adder, implemented using a structural modeling approach:

📊 Block Diagram

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First, we define a 1-bit full adder using logic gate primitives:

// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);// I/O port declarations
output sum, c_out;
input a, b, c_in;// Internal nets
wire s1, c1, c2;// Instantiate logic gate primitives
xor (s1, a, b);
and (c1, a, b);xor (sum, s1, c_in);
and (c2, s1, c_in);or (c_out, c2, c1);endmodule

Next, we build a 4-bit full adder by cascading four 1-bit full adders:

// Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);// I/O port declarations
output [3:0] sum;
output c_out;
input [3:0] a, b;
input c_in;// Internal nets
wire c1, c2, c3;// Instantiate four 1-bit full adders
fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3], c3);endmodule

Explanation:

• The 1-bit full adder computes sum and carry using basic logic gates (XOR, AND, OR).
• Intermediate signals (s1, c1, c2) help implement the full adder equations.
• The 4-bit adder is built by cascading four 1-bit full adders.
• The carry-out from each stage is connected to the carry-in of the next stage.
• This structure is known as a ripple carry adder, as the carry “ripples” through each stage.

Conclusion

This Verilog implementation of a 4-bit Full Adder demonstrates how complex arithmetic circuits can be built using smaller building blocks. The ripple carry approach is simple and widely used, though it introduces propagation delay as the carry moves through each stage.

What’s Next?

Try simulating this design and observe how carry propagates across stages. In the next post, we’ll explore more efficient adder designs and their Verilog implementations.

Happy Coding! 🚀