Mastering Verilog: Implementing a Half Subtractor

 Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Half Subtractor in Verilog. A half subtractor is a combinational circuit used to subtract two single-bit binary numbers and produce a Difference and a Borrow as outputs.
It is a fundamental building block in digital arithmetic circuits.

Below is the Verilog code for a Half Subtractor, implemented using a Behavioral Modeling approach:

📊 Block Diagram

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In the behavioral modeling approach, we define the output using simple logical expressions based on the input values.

module half_subtractor(input a, b, output D, B);
  assign D = a ^ b;
  assign B = ~a & b;
endmodule

🧪 Testbench

module tb_top;
  reg a, b;
  wire D, B;
  
  half_subtractor hs(a, b, D, B);
  
  initial begin
    $monitor("At time %0t: a=%b b=%b, difference=%b, borrow=%b",$time, a,b,D,B);
    a = 0; b = 0;
    #1;
    a = 0; b = 1;
    #1;
    a = 1; b = 0;
    #1;
    a = 1; b = 1;
  end
endmodule

Explanation:

• The Difference (D) is calculated using the XOR operation between inputs a and b.
• The Borrow (B) is generated when a is 0 and b is 1, implemented as ~a & b.
• The design is purely combinational and updates output instantly with input changes.
• The testbench verifies all possible input combinations.

Conclusion

This Verilog implementation of a Half Subtractor demonstrates how basic arithmetic operations can be modeled using simple logic expressions. It serves as a foundation for designing more complex circuits like full subtractors.

What’s Next?

Try extending this design to a Full Subtractor and observe how borrow propagation works. In the next post, we’ll explore more arithmetic circuits and their Verilog implementations.

Happy Coding! 🚀