Mastering Verilog: Implementing a Full Subtractor

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Full Subtractor in Verilog. A full subtractor is a combinational circuit used to subtract three bits: two significant bits and a borrow-in, producing a Difference and a Borrow-out.

It is an essential component in digital arithmetic circuits and forms the basis for multi-bit subtraction.

Below is the Verilog code for a Full Subtractor, implemented using a Behavioral Modeling approach:

📊 Block Diagram

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In the behavioral modeling approach, we define the outputs using logical expressions based on the inputs.

module full_subtractor(input a, b, Bin, output D, Bout);
  assign D = a ^ b ^ Bin;
  assign Bout = (~a & b) | (~(a ^ b) & Bin);
endmodule

🧪 Testbench

module tb_top;
  reg a, b, Bin;
  wire D, Bout;
  
  full_subtractor fs(a, b, Bin, D, Bout);
  
  initial begin
    $monitor("At time %0t: a=%b b=%b, Bin=%b, difference=%b, borrow=%b",$time, a,b,Bin,D,Bout);
    a = 0; b = 0; Bin = 0; #1;
    a = 0; b = 0; Bin = 1; #1;
    a = 0; b = 1; Bin = 0; #1;
    a = 0; b = 1; Bin = 1; #1;
    a = 1; b = 0; Bin = 0; #1;
    a = 1; b = 0; Bin = 1; #1;
    a = 1; b = 1; Bin = 0; #1;
    a = 1; b = 1; Bin = 1;
  end
endmodule

Explanation:

• The Difference (D) is calculated using XOR operations among a, b, and Bin.
• The Borrow-out (Bout) is generated when subtraction requires borrowing, based on input conditions.
• The design is purely combinational, meaning outputs change instantly with inputs.
• The testbench verifies all possible input combinations.

Conclusion

This Verilog implementation of a Full Subtractor demonstrates how multi-bit subtraction can be handled using combinational logic. It is a key building block for more complex arithmetic units.

What’s Next?

Try extending this to a multi-bit subtractor and observe borrow propagation across stages. In the next post, we’ll explore more arithmetic circuits and their Verilog implementations.

Happy Coding! 🚀