Mastering Verilog: Implementing a Priority Encoder

Welcome to another edition of our Verilog series! In this blog post, we’ll explore the implementation of a Priority Encoder in Verilog. A Priority Encoder is a combinational circuit that outputs the binary representation of the highest-priority active input when multiple inputs are high simultaneously.

This type of encoder is widely used in digital systems such as interrupt controllers, arbitration logic, and resource allocation where priority-based decision-making is required.

Below is the Verilog code for a Priority Encoder, implemented using a Behavioral Modeling approach:

📊 Truth Table

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In the behavioral modeling approach, we define priority using ordered conditional statements, where the first true condition gets the highest priority.

module alarm_priority_1 (output [2:0] intruder_zone,
                         output       valid,
                         input  [1:8] zone );assign intruder_zone = zone[1] ? 3'b000 :
                       zone[2] ? 3'b001 :
                       zone[3] ? 3'b010 :
                       zone[4] ? 3'b011 :
                       zone[5] ? 3'b100 :
                       zone[6] ? 3'b101 :
                       zone[7] ? 3'b110 :
                       zone[8] ? 3'b111 :
                       3'b000;assign valid = zone[1] | zone[2] | zone[3] | zone[4] |
               zone[5] | zone[6] | zone[7] | zone[8];endmodule

Explanation:

• The encoder checks inputs from zone[1] to zone[8] in order, assigning priority from lowest index to highest.
• If multiple inputs are high, the first active input in the sequence is selected.
• The intruder_zone output provides the binary index of the highest-priority active input.
• The valid signal indicates whether any input is active.
• If no inputs are active, valid becomes 0 and the output defaults to 000.

Conclusion

This Verilog implementation of a Priority Encoder demonstrates how priority logic can be modeled using simple conditional statements. Such designs are essential in systems where multiple requests compete and only the highest-priority request should be processed.

What’s Next?

Try simulating this design with different input combinations to observe how priority is resolved. In the next post, we’ll explore more advanced digital circuits and their Verilog implementations.

Happy Coding! 🚀